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The Design of DC-DC Converter with DTMOS Switch
Yongseo Koo,Kasan Ha,Kwangyeob Lee,Jaechang Kwak,Kuidong Kim,Jongki Kwon 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
The high efficiency power management IC(PMIC) with switching device is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS(Dynamic Threshold voltage MOSFET) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DTMOS drops as the gate voltage increases, resulting in a much higher current handling capability than standard MOSFET. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Sawtooth generator is made to have 1.2 ㎒ oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70㏈ DC gain and 64° phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low onresistance switching device, achieved the high efficiency near 95% at 100㎃ output current.
Low Ron and high robustness ESD protection design for low-voltage power clamp application
Song, BoBae,Koo, YongSeo IET 2016 Electronics letters Vol.52 No.18
<P>An electrostatic discharge (ESD) protection circuit with novel structure based on a silicon-controlled rectifier (SCR) is proposed for 5 V ESD protection of integrated circuits. The proposed ESD protection circuit has large current driving capacity due to its low on-resistance and high ESD robustness in comparison with the conventional SCR-based ESD protection circuit. The conventional SCR-based ESD protection circuit and the proposed ESD protection circuit were fabricated using a 0.18 mu m bipolar CMOS-double diffused metal-oxide semiconductor transistor (DMOS) process, and their electrical characteristics and ESD robustness were comparatively analysed using transmission line pulse measurements.</P>
A Low-Voltage-Triggering-Dual-directional SCR Device for ESD Protection
Kwangyeob Lee,Jungman Son,Yongseo Koo,Jaechang Kwak,Kuidong Kim,Jongki Kwon 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
A low-voltage triggering dual-directional silicon controlled rectifier(SCR) device for ESD Protection of advanced low voltage CMOS application was proposed and studied using numerical simulation. The device is capable of providing effective protection for ICs against ESD stresses in the two opposite directions without division of anode and cathode) and the device has area efficiency. Comparing with the conventional dualdirectional SCR, the proposed device has low trigger voltage than conventional device because of added NMOS structure inside proposed device. In the simulation result, the triggering voltage of the device is 6V~9V and the holding voltage is 2.2V~ 4.2V with variation of design parameter, respectively. And the device has same robustness compared to conventional one.
신사무엘(Samuell Shin),손정만(Jungman Son),구용서(Yongseo Koo) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This study is presented about electrical characteristics of 2500V planar gate IGBT The breakdown voltage and saturation voltage (Vce, sat) according to variations of gate length, emitter window region, and drift region depth were simulated using 2D simulator (MEDICI). In simulation results, when the gate length was 15㎛, the emitter window region was 8㎛ and drift region depth was 375㎛, the breakdown voltage and saturation voltage (Vce, sat) of optimized IGBT were simulated to 2810V, 3.4V respectively.
Analysis of the IGBT with improved trade-off characteristic between conduction and turn-off losses
Samuell Shin,Jongil Won,Kuidong Kim,Jongki Kwon,Yongseo Koo 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, we tried different two approach to improve the performance of the IGBT. The first approach is that adding N+ region beside P-base in the conventional IGBT. It can make the conventional IGBT to get faster turn-off time and lower conduction loss. The second approach is that adding P+ region on right side under gate to improve latching current of conventional IGBT. The device simulation results show improved on-state, latch-up and switching characteristics in each structure. The first one was presented lower voltage drop(3.08V) and faster turn-off time(3.4us) than that of conventional one(3.66V/3.65us). Also, second structure has higher latching current(369A/㎠) that of conventional structure. Finally, we present a novel IGBT combined the first approach with second one for improved trade-off characteristic between conduction and turn-off losses. The proposed device has better performance than conventional IGBT.
The novel high voltage IGBT with improved on-resistance and turn-off characteristics
Mankoo Lee,Samuell Shin,Kasan Ha,Kangyoon Lee,Yongseo Koo 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, the novel 2.5KV IGBT incorporating an n-type MOSFET between adjacent cells is proposed with the aim of the improving the tradeoff relation between switching time and conduction loss. The incorporated MOSFET provides an additional base current that led to the increase of collector current of IGBT and the decrease of the on-state voltage drop. Also, the turn-off time and the static latch-up susceptibility are decreased because of the P+ region of the incorporated MOSFET, In the experimental result, with incorporating an n-type MOSFET, the turn-off time and on-state voltage drop are decreased by approximately 8% and 15% respectively, compared to a conventional IGBT. And the proposed IGBT provides higher latching current of 39% than conventional IGBT.
낮은 대기전류 및 빠른 과도응답특성을 갖는 LDO 레귤레이터
권상욱(Sang-Wook Kwon),도경일(Kyoung-Il Do),서정주(Jeong-Ju Seo),우제욱(Jae Wook Woo),구용서(YongSeo Koo) 대한전자공학회 2019 대한전자공학회 학술대회 Vol.2019 No.6
This paper present a Low Drop Out regulator (LDO) that improves the road transient response characteristics by using a voltage regulator. A voltage regulator circuit is placed between the error amplifier and the pass transistor inside the LDO regulator to improve the current characteristics of the voltage line, The proposed Fast Transient LDO structure was designed by a 0.18 um process with Cadence’s Virtuoso simulation. According to test results, the proposed circuit has a improved transient characteristics compare with conventional LDO. The simulation results show that the transient of rising increases from –836.2uV to –123.3uV and the transient of falling decreases from 913.1uV to 715.8uV compared with conventional LDO.