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Real-time comprehensive image processing system for detecting concrete bridges crack
Weiguo Lin,Yichao Sun,Qiaoning Yang,Yaru Lin 사단법인 한국계산역학회 2019 Computers and Concrete, An International Journal Vol.23 No.6
Cracks are an important distress of concrete bridges, and may reduce the life and safety of bridges. However, the traditional manual crack detection means highly depend on the experience of inspectors. Furthermore, it is time-consuming, expensive, and often unsafe when inaccessible position of bridge is to be assessed, such as viaduct pier. To solve this question, the real-time automatic crack detecting system with unmanned aerial vehicle (UAV) become a choice. This paper designs a new automatic detection system based on real-time comprehensive image processing for bridge crack. It has small size, light weight, low power consumption and can be carried on a small UAV for real-time data acquisition and processing. The real-time comprehensive image processing algorithm used in this detection system combines the advantage of connected domain area, shape extremum, morphology and support vector data description (SVDD). The performance and validity of the proposed algorithm and system are verified. Compared with other detection method, the proposed system can effectively detect cracks with high detection accuracy and high speed. The designed system in this paper is suitable for practical engineering applications.
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Yinyu Yan,Yichao Sun,Wanxin Guo,Hao Jiang,Minqiang Hu 전력전자학회 2024 JOURNAL OF POWER ELECTRONICS Vol.24 No.6
Modular multilevel converter-based solid-state transformers (MMC-SST) usually use the input series output parallel structure or the dual active bridge (DAB) structure. These two structures suffer from low power supply reliability and high economic costs, respectively. Therefore, based on hybrid frequency modulation, this paper proposes an arm integrated double capacitor submodule (AIDCSM)-type MMC-SST topology. This topology effectively reduces the number of switching devices by integrating the submodule arms, while enabling the topology to possess DC short-circuit fault ride-through capability. When compared to the DAB-type MMC-SST with half-bridge submodules, the proposed AIDCSM-type MMC-SST saves 2/5 switching devices and 1/2 high-frequency transformers, and enables uninterrupted operation under DC short-circuit faults. At the same time, the control strategy of the proposed AIDCSM-type MMC-SST is thoroughly investigated under both normal operating and DC short-circuit conditions. Simulation and experimental results demonstrate the correctness and effectiveness of the proposed topology and control method.
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Ji, Zhendong,Zhao, Jianfeng,Sun, Yichao,Yao, Xiaojun,Zhu, Zean The Korean Institute of Power Electronics 2014 JOURNAL OF POWER ELECTRONICS Vol.14 No.5
Cascaded H-Bridge (CHB) converters can be directly connected to medium-voltage grids without using transformers and they possess the advantages of large capacity and low harmonics. They are significant tools for providing grid connections in large-capacity renewable energy systems. However, the reliability of a grid-connected CHB converter can be seriously influenced by the number of power switching devices that exist in the structure. This paper proposes a fault-tolerant control strategy based on double zero-sequence voltage injection and DC voltage optimization to improve the reliability of star-connected CHB converters after one or more power units have been bypassed. By injecting double zero-sequence voltages into each phase cluster, the DC voltages of the healthy units can be rapidly balanced after the faulty units are bypassed. In addition, optimizing the DC voltage increases the number of faulty units that can be tolerated and improves the reliability of the converter. Simulations and experimental results are shown for a seven-level three-phase CHB converter to validate the efficiency and feasibility of this strategy.
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Zhendong Ji,Jianfeng Zhao,Yichao Sun,Xiaojun Yao,Zean Zhu 전력전자학회 2014 JOURNAL OF POWER ELECTRONICS Vol.14 No.5
Cascaded H-Bridge (CHB) converters can be directly connected to medium-voltage grids without using transformers and they possess the advantages of large capacity and low harmonics. They are significant tools for providing grid connections in large-capacity renewable energy systems. However, the reliability of a grid-connected CHB converter can be seriously influenced by the number of power switching devices that exist in the structure. This paper proposes a fault-tolerant control strategy based on double zero-sequence voltage injection and DC voltage optimization to improve the reliability of star-connected CHB converters after one or more power units have been bypassed. By injecting double zero-sequence voltages into each phase cluster, the DC voltages of the healthy units can be rapidly balanced after the faulty units are bypassed. In addition, optimizing the DC voltage increases the number of faulty units that can be tolerated and improves the reliability of the converter. Simulations and experimental results are shown for a seven-level three-phase CHB converter to validate the efficiency and feasibility of this strategy.
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Yet another Hybrid Strategy for Auto-tuning SpMV on GPUs
Zhaohui Wang,Xiaojie Qiu,Aimin Zhang,Yichao Cheng,Yi Peng,Sun Sun 보안공학연구지원센터 2015 International Journal of Software Engineering and Vol.9 No.5
Sparse matrix-vector multiplication (SpMV) is a key linear algebra algorithm and is widely used in many application domains. Besides multi-core architecture, there is also extensive research focusing on accelerating SpMV on many-core Graphics Processing Units (GPUs). SpMV computations have many indirect and irregular memory accesses, and load imbalance could occur while mapping computations onto single-instruction, multiple-data (SIMD) GPUs. SpMV is highly memory bandwidth-bound, though GPUs have massive computational resources, the performance of SpMV on GPUs is still unsatisfying. In this paper, we present a new hybrid strategy for auto-tuning SpMV on GPUs. Our strategy combines the advantages of row-major storage and column-major storage. Like many other strategies, we reordered a given sparse matrix according to row lengths in decreasing order. In order to be more adaptive and efficient, we proposed a new hybrid Blocked CSR and JDS (BCJ) format based on original CSR and JDS. BCJ splits a sparse matrix into a denser part and a sparser part after reordering and uses different kernels to process the corresponding part. And we proposed corresponding auto-tuning framework to help transforming matrix and launching kernels according to the sparsity characteristics of the matrix. A CUDA implementation of BCJ outperforms the original formats significantly on a broad range of unstructured sparse matrices.
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