http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Vanshaj Taxali (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
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LVCMOS Based Energy Efficient Sindhi Unicode Reader for Natural Processing on 28nm FPGA
Shivani Madhok,Inderpreet Kaur,Vanshaj Taxali,Vandana Thind,Sweety Dabas,Tushar Madhok 보안공학연구지원센터 2015 International Journal of u- and e- Service, Scienc Vol.8 No.8
In this research work, we have focused on designing an energy efficient Sindhi Unicode reader based on LVCMOS for natural processing. Unicode is a standard for a universal character set for all the scripts of the world. It is one of the fundamental technological building blocks for exchanging textual information internationally, via computers. The scripts of Sindh are Brahmi-based writing systems. Our main aim of this paper is to build an energy efficient low power design for this we have taken different frequencies and calculated its power. We have done power analysis on a constant temperature that is 25 degree Celsius and also keeping air flow constant. We have varied frequency and calculated power for different LVCMOS IO STANDARDs. Our design is based on 28nm FPGA and the code has been tested on Kintex-7 and the device used is XC7K160T, package used is FBG676 and it is working on -3 speed grade. At the end we have concluded that there is 3.27%, 3.38%, 4.34%, 3.12%, 4.54%, 4.28% saving in power dissipation with LVCMOS18 and LVCMOS15 when compared with LVCMOS33 at 1400 MHz, 1.2 GHz, 2100 MHz, 1700 MHz, 1800MHz, 2.2 GHz respectively.
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FPGA Based Energy Efficient Universal Asynchronous Receiver Transmitter Design Using Thermal Scaling
Rashmi Sharma,Shivani Sharma,Paresh Khaneja,Navya Bhasin,Vanshaj Taxali 보안공학연구지원센터 2015 International Journal of Smart Home Vol.9 No.6
This paper throws light on the behavior of the UART in response to the variations in the junction temperature. Analysis has been done to find the most ideal temperature range for the operation of the UART. After all the calculations, deduction comes to a point that lowering the temperature values increases the efficiency of the UART significantly since the losses due to the leakage power are reduced to a minimum value when the temperature is decreased. Significant reduction in the percentage of leakage power is seen as the temperature is lowered. Implementation has been done on the FPGA generations Virtex-6, Virtex-5, Virtex-4 using XILINX simulator and Verilog Hardware Description Language. Different reduction percentages have been observed within a range of 8% to 37.4% for the leakage power and 16.8% to 69.3%for the ambient temperature as the results are obtained for frequency values of 1GHz and 1MHz. Thus various power loss parameters have been studied to get the best energy efficient UART.
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