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Sandip Bhattacharya,Mohammed Imran Hussain,John Ajayan,Shubham Tayal,Louis Maria Irudaya Leo Joseph,Sreedhar Kollem,Usha Desai,Syed Musthak Ahmed,Ravichander Janapati 한국전자통신연구원 2023 ETRI Journal Vol.45 No.5
In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.
Muchahary Deboraj,Ram Lakum Sai,Narzary Rewrewa,Sahu Partha Pratim,Bhattarai Sagar,Tayal Shubham 한국물리학회 2022 Current Applied Physics Vol.38 No.-
In this work coupled ZnO⋅SnO2 nanocomposite has been used as heterojunction partner to Si for photovoltaic application and its performance is optimized. The interface defect more than 1012 cm-2 reduces the short circuit current density, fill factor and efficiency of the device. In addition, the best device performance is observed at the vicinity of 280K. The junction of the device has a dark saturation current density and ideality factor of the order of 10-4 Acm-2 and 21 respectively. In addition, four different organic materials are used as back surface field layer (BSL) to the same device and performance is improved. The best conversion efficiency and open circuit voltage as high as 4.1% and 0.591 V respectively are obtained for the device with CuSCN as BSL. Consequently, a range of combined values of the energy band gap and electron affinity of the BSL materials are examined for optimal device performance.