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Hierarchy Structure of Dynamically Reconfigurable Circuit for MP3 Decoder
Kiyotaka Komoku,Takayuki Morishita 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this study, we proposed hierarchy structure of dynamically reconfigurable circuit for MP3 (MPEG-1 Audio Layer Ⅲ) decoder. Suitable composition of Unit group, that is basic structure of the circuit, was investigated. Target application circuits are dequantization, antialiasing and IMDCT processing in MP3 decoding process. Suitable UG was decided, that has five register units, two multiply units, two addition/subtraction units, and two counter units. For configuring three application circuits using this UG, four UG is needed.
Study of a Suitable Structure of Dynamically Reconfigurable VLD Circuit for MP3 Decoding
Kiyotaka Komoku,Takashi Miyake,Takayuki Morishita,Nobuo Sasaki 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
We have been proposed a VLD architecture that includes many comparators and can reconfigure the circuit structure adaptively, corresponding to VLC table number. For analyzing performance of the circuit, a functional simulation program of the proposed VLD circuit was developed. In this paper, we show the output result of the simulation program.