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Reliability Characteristics of La-doped High-k/Metal Gate nMOSFETs
C. Y. Kang,R. Choi,B. H. Lee,R. Jammy 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.3
The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower Vth and Igate, which is attributed to the dipole formation at the high-k/SiO₂ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (ΔVth) at high field PBTI is significant. The results of a transconductance shift (ΔGm) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.
Reliability Characteristics of La-doped High-k/Metal Gate nMOSFETs
Kang, C.Y.,Choi, R.,Lee, B.H.,Jammy, R. The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.3
The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.
Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric
Hyun-Sik Choi,Seung-Ho Hong,Rock-Hyun Baek,Kyong-Taek Lee,Chang-Yong Kang,Jammy, R.,Byoung-Hun Lee,Sung-Woo Jung,Yoon-Ha Jeong IEEE 2009 IEEE electron device letters Vol.30 No.5
<P>Low-frequency noise (LFN) after channel soft oxide breakdown (SBD) of n-MOSFETs with a HfLaSiO gate dielectric and TaN metal gate shows a Lorentzian-like spectrum, which is not observed in HfSiO gate dielectric devices after channel SBD. This is related to the spatial location of the SBD spot. Because La weakens atomic bonding in the interface layer, the SBD spot is generated close to the Si/SiO<SUB>2</SUB> interface. This is verified by using time domain analysis. To examine the property of this Lorentzian-like noise, LFNs after channel SBD are measured repeatedly after arbitrary times. After about 20 h, LFN finally shows an increase only at the low-frequency part of the noise spectrum (f < 1 kHz). These results suggest that the trap distribution after arbitrary times spreads instead of remaining localized. Therefore, the traps or the La-O defect clusters have severe unstable distribution and induce an increase of the localized field, which, in turn, causes the traps to percolate through the high-k dielectric.</P>
Yoo, O.S.,Oh, J.,Kang, C.Y.,Lee, B.H.,Han, I.S.,Choi, W.H.,Kwon, H.M.,Na, M.K.,Majhi, P.,Tseng, H.H.,Jammy, R.,Wang, J.S.,Lee, H.D. Elsevier Sequoia 2008 Materials science & engineering. B, Advanced funct Vol.154 No.-
We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO<SUB>2</SUB>/TaN. Ge outdiffusion and oxygen interdiffusion were completely suppressed by thick Si interfacial layer. As a result, formation of insufficient low-k Ge oxides was effectively inhibited. It is confirmed that gate current of Si passivated Ge MOS was decreased by Si IL and decrease of gate current, J<SUB>g</SUB> is saturated after Si IL of 2nm. It was also observed that when Si IL is thick enough to restrict Ge outdiffusion, increase of J<SUB>g</SUB> is not due to the temperature-induced Ge outdiffusion but due to the partial crystallization of HfO<SUB>2</SUB> at higher annealing temperature.
Chang-Woo Sohn,Hyun Chul Sagong,Eui-Young Jeong,Do-Young Choi,Min Sang Park,Jeong-Soo Lee,Chang Yong Kang,Jammy, R,Yoon-Ha Jeong IEEE 2011 IEEE electron device letters Vol.32 No.4
<P>In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO<SUB>2</SUB> and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO<SUB>2</SUB> bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The model's effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.</P>
Ying-Ying Zhang,Jungwoo Oh,Shi-Guang Li,Soon-Yen Jung,Kee-Young Park,Ga-Won Lee,Majhi, P.,Hsing-Huang Tseng,Jammy, R.,Hi-Deok Lee IEEE 2010 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.9 No.2
<P>In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 <SUP>°</SUP>C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as Pt<SUB>x</SUB>Ge<SUB>y</SUB> and Ni<SUB>x</SUB>Pt<SUB>1-x</SUB>Ge<SUB>y</SUB> can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.</P>
Hyuk-Min Kwon,In-Shik Han,Jung-Deuk Bok,Sang-Uk Park,Yi-Jung Jung,Ga-Won Lee,Yi-Sun Chung,Jung-Hwan Lee,Chang Yong Kang,Kirsch, P,Jammy, R,Hi-Deok Lee IEEE 2011 IEEE electron device letters Vol.32 No.5
<P>The behavior of I<SUB>D</SUB> random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO<SUB>2</SUB>/TaN is experimentally investigated and discussed. The I<SUB>D</SUB>-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of I<SUB>D</SUB>-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔI<SUB>D</SUB>/I<SUB>D</SUB>) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, I<SUB>D</SUB>-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.</P>
Ying-Ying Zhang,Jungwoo Oh,In-Shik Han,Zhun Zhong,Shi-Guang Li,Soon-Yen Jung,Kee-Young Park,Hong-Sik Shin,Won-Ho Choi,Hyuk-Min Kwon,Wei-Yip Loh,Majhi, P.,Jammy, R.,Hi-Deok Lee IEEE 2009 IEEE transactions on electron devices Vol.56 No.2
<P>Highly thermally stable Ni germanide technology for high performance germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs) is proposed, utilizing Pd incorporation into Ni germanide. The proposed Ni germanide shows not only the improvement of thermal stability but also the reduction of hole barrier height, which can improve the device on-current by reducing the Ni germanide to p+ source/drain contact resistance. The proposed Ni germanide showed a stable sheet resistance of up to 500 degrees C 30-min postgermanidation annealing due to the suppression of agglomeration and oxidation of Ni germanide and the diffusion of Ni and Ge atoms by the incorporated Pd. Therefore, the proposed Ni0.95Pd0.05, alloy could be promising for the high mobility Ge MOSFET applications.</P>
In-Shik Han,Won-Ho Choi,Hyuk-Min Kwon,Min-Ki Na,Ying-Ying Zhang,Yong-Goo Kim,Jin-Suk Wang,Chang Yong Kang,Bersuker, G.,Byoung Hun Lee,Yoon Ha Jeong,Hi-Deok Lee,Jammy, R. IEEE 2009 IEEE electron device letters Vol.30 No.3
<P>Time-dependent dielectric breakdown (TDDB) characteristics of La<SUB>2</SUB>O<SUB>3</SUB>-doped high-k dielectric in Hf-based high-k/TaN metal gate stack were studied. Unlike the abrupt breakdown in the conventional SiO<SUB>2</SUB> , dielectric breakdown behaviors of La-incorporated HfON and HfSiON dielectrics show progressive breakdown characteristics. Moreover, the extracted Weibull slope beta of breakdown distribution is in the range of 0.87-1.19, and it is independent on capacitor areas and stress conditions. Moreover, field dependence of T<SUB>BD</SUB> and stress-induced leakage current strongly suggest that the E-model is more applicable to explain in TDDB of La-incorporated high-k dielectric in Hf-based high-k/metal gate stack structure.</P>