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Piersanti, Stefano,de Paulis, Francesco,Olivieri, Carlo,Jung, Daniel H.,Kim, Joungho,Orlandi, Antonio [Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.5
<P>Small form factors and high bandwidth are two imperatives nowadays for three-dimensional integrated circuits (3-D-ICs). These requirements can be achieved by the use of through silicon vias, by the reduction of their radius and, at the same time, of the pitch among them. Having a considerable number of devices in a limited space inevitably increases the probability of the creation of defects (short, open, void, etc.). The study of the nature, topology, and creation mechanism of defects is crucial for 3-D-IC design. This paper suggests a procedure able to determine the nature of a defect (open-or short-circuit) and to estimate its position, basing its approach on the study of the electrical parameters of the defected structure, avoiding the use of invasive method such as Lock-in Thermography. A daisy-chain structure is manufactured and open or short defects are intentionally placed along the channel. With and without defects, the equivalent capacitance and inductance are extracted from the S-Parameters, from measurement and three-dimensional electromagnetic simulations, and used to define and validate the proposed procedure.</P>
Budget Deficits and Exchange-Rate Crises
BARBARA ANNICCHIARICO,GIANCARLO MARINI,GIOVANNI PIERSANTI 한국국제경제학회 2011 International Economic Journal Vol.25 No.2
This paper investigates currency crises in an optimizing general equilibrium model with overlapping generations. It is shown that a rise in government budget deficits financed by future taxes generates a decumulation of external assets, leading up to a speculative attack and forcing the monetary authorities to abandon the peg.
Through-Silicon Via Capacitance–Voltage Hysteresis Modeling for 2.5-D and 3-D IC
Kim, Dong-Hyun,Kim, Youngwoo,Cho, Jonghyun,Bae, Bumhee,Park, Junyong,Lee, Hyunsuk,Lim, Jaemin,Kim, Jonghoon J.,Piersanti, Stefano,de Paulis, Francesco,Orlandi, Antonio,Kim, Joungho IEEE 2017 IEEE transactions on components, packaging, and ma Vol.7 No.6
<P>We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.</P>
Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis
Jung, Daniel H.,Youngwoo Kim,Kim, Jonghoon J.,Heegon Kim,Sumin Choi,Yoon-Ho Song,Hyun-Cheol Bae,Kwang-Seong Choi,Piersanti, Stefano,de Paulis, Francesco,Orlandi, Antonio,Joungho Kim IEEE 2017 IEEE transactions on components, packaging, and ma Vol.7 No.1
<P>Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 mu m and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with S-parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, S-11 is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. S-parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the S-parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.</P>