Designing Fault-Tolerant Photovoltaic Systems

Xue Lin,Yanzhi Wang,Pedram, Massoud,Jaemin Kim,Naehyuck Chang IEEE Computer Society 2014 IEEE design & test Vol.31 No.3

<P>PV systems are subject to PV cell faults, which lower the output power and shorten the lifespan of the system. This paper presents the design principles and runtime control algorithms of a fault-tolerant PV system which can detect and bypass PV cell faults in situ without any manual interventions.</P>

Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting

Lin, Xue,Wang, Yanzhi,Chang, Naehyuck,Pedram, Massoud IEEE 2016 IEEE transactions on computer-aided design of inte Vol.35 No.11

<P>Energy harvesting is a promising technique to overcome the limit on energy availability and increase the lifespan of battery-powered embedded systems. In this paper, the question of how one can achieve the prolonged lifespan(1) of a real-time embedded system with energy harvesting capability (RTES-EH) is investigated. The RTES-EH comprises a photovoltaic (PV) panel for energy harvesting, a supercapacitor for energy storage, and a real-time sensor node as the embedded load device. A global controller performs simultaneous optimal operating point tracking for the PV panel, state-of-charge (SoC) management for the supercapacitor, and energy-harvesting-aware real-time task scheduling with dynamic voltage and frequency scaling (DVFS) for the sensor node, while employing a precise solar irradiance prediction method. The controller employs a cascaded feedback control structure, where an outer supervisory control loop performs real-time task scheduling with DVFS in the sensor node while maintaining the optimal supercapacitor SoC for improved system availability, and an inner control loop tracks the optimal operating point of the PV panel on the fly. Experimental results show that the proposed global controller lowers the task instance drop rate by up to 63% compared with the baseline controller within the same service time (i.e., from sunrise to sunset).</P>

High-Efficiency, Auto Mode-Hop, Variable-Voltage, Ripple Control Buck Converter

Ehsan Rokhsat-Yazdi,Ali Afzali-Kusha,Massoud Pedram 전력전자학회 2010 JOURNAL OF POWER ELECTRONICS Vol.10 No.2

In this paper, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed. The converter, which operates under a wide range of input and output voltages, makes use of a statedependent hysteretic comparator. Depending on the output current, the converter automatically changes the operating mode. This improves the efficiency and reduces the output voltage ripple for a wide range of output currents for given input and output voltages. The sensitivity of the output voltage to the circuit elements is less than 14%, which is seven times lower than that for conventional converters. To assess the efficiency of the proposed converter, it is designed and implemented with commercially available components. The converter provides an output voltage in the range of 0.9V to 31V for load currents of up to 3A when the input voltage is in the range of 5V to 32V. Analytical design expressions which model the operation of the converter are also presented. This circuit can be implemented easily in a single chip with an external inductor and capacitor for both fixed and variable output voltage applications.

Flexible Prime-Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

Hamid-Reza Ahmadi,Ali Afzali-Kusha,Massoud Pedram,Mahdi Mosaffa 한국전자통신연구원 2015 ETRI Journal Vol.37 No.1

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 m standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only 6.55 J of energy (average power consumption is 12.76 W). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use

Zhu, Di,Yue, Siyu,Chang, Naehyuck,Pedram, Massoud IEEE 2016 IEEE transactions on computer-aided design of inte Vol.35 No.7

<P>Hybrid electrical energy storage (HEES) systems have the potential to result in considerable cost savings by reducing the electric bills of home users. This paper first presents grid-connected dual-bank HEES system design and management to maximize the electric bill savings for residential users, and subsequently provides a comprehensive sensitivity analysis of the economic feasibility of residential HEES systems. Specifically, the paper describes a daily management policy based on energy buffering strategy with one bank as the main storage bank and the other as the energy buffering bank, and then derive the global design of HEES specifications based on the daily management results. Simulation results prove the effectiveness of energy buffering strategy and show the proposed HEES system is capable of bringing in profits under current input variables. Finally, a detailed analysis is conducted to show how each input variable affects the final design of the proposed residential HEES system and the maximum annual profits it achieves. Together with the design and control mechanism, the proposed analysis provides potential customers with the comprehensive knowledge of how HEES systems can be deployed to achieve savings in their electric bills.</P>

A High-Efficiency, Auto Mode-Hop, Variable-Voltage, Ripple Control Buck Converter

Rokhsat-Yazdi, Ehsan,Afzali-Kusha, Ali,Pedram, Massoud The Korean Institute of Power Electronics 2010 JOURNAL OF POWER ELECTRONICS Vol.10 No.2

In this paper, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed. The converter, which operates under a wide range of input and output voltages, makes use of a state-dependent hysteretic comparator. Depending on the output current, the converter automatically changes the operating mode. This improves the efficiency and reduces the output voltage ripple for a wide range of output currents for given input and output voltages. The sensitivity of the output voltage to the circuit elements is less than 14%, which is seven times lower than that for conventional converters. To assess the efficiency of the proposed converter, it is designed and implemented with commercially available components. The converter provides an output voltage in the range of 0.9V to 31V for load currents of up to 3A when the input voltage is in the range of 5V to 32V. Analytical design expressions which model the operation of the converter are also presented. This circuit can be implemented easily in a single chip with an external inductor and capacitor for both fixed and variable output voltage applications.

Principles and Efficient Implementation of Charge Replacement in Hybrid Electrical Energy Storage Systems

Qing Xie,Younghyun Kim,Yanzhi Wang,Jaemin Kim,Naehyuck Chang,Pedram, Massoud IEEE 2014 IEEE TRANSACTIONS ON POWER ELECTRONICS - Vol.29 No.11

<P>Hybrid electrical energy storage systems (HEES) are comprised of multiple banks of inhomogeneous EES elements with difference characteristics. They have been proposed to achieve desired performance metrics of an ideal energy storage device, i.e., high energy capacity, high output power level, low self-discharge, low cost, and long service life. Implementation of appropriate charge management policies enables efficient storage and retrieval of the electrical energy, attaining performance metrics that are close to the respective best values across the constituent EES elements in the HEES system. This paper addresses a global charge replacement problem in HEES systems, namely, how to dynamically select a subset of the EES banks and discharge them to meet the load power demand in a prespecified amount of time. Precisely, the global charge replacement optimization problem is formulated as a mixed-integer nonlinear programming problem, and a hierarchical algorithm is presented to efficiently solve this problem. At the top level the proposed algorithm considers the complete discharging process and allocates the load demand among all available EES banks, whereas at the bottom level it employs convex optimization methods to solve for discharging currents and the voltage level of a shared charger transfer interconnect. A prototype HEES system has been built to demonstrate the energy benefits brought by HEES systems and the efficacy of the proposed charge replacement algorithm.</P>

TEI-power : Temperature Effect Inversion--Aware Dynamic Thermal Management

Lee, Woojoo,Han, Kyuseung,Wang, Yanzhi,Cui, Tiansong,Nazarian, Shahin,Pedram, Massoud Association for Computing Machinery 2017 Transactions on Design Automation of Electronic Sy Vol.22 No.3

<P>FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm technology nodes. However, based on the temperature effect inversion (TEI) phenomenon observed in FinFET devices, the delay characteristics of FinFET circuits in sub-, near-, and superthreshold voltage regimes may be fundamentally different from those of CMOS circuits with nominal voltage operation. For example, FinFET circuits may run faster in higher temperatures. Therefore, the existing CMOS-based and TEI-unaware dynamic power and thermal management techniques would not be applicable. In this article, we present TEI-power, a dynamic voltage and frequency scaling-based dynamic thermal management technique that considers the TEI phenomenon and also the superlinear dependencies of power consumption components on the temperature and outlines a real-time trade-off between delay and power consumption as a function of the chip temperature to provide significant energy savings, with no performance penalty-namely, up to 42% energy savings for small circuits where the logic cell delay is dominant and up to 36% energy savings for larger circuits where the interconnect delay is considerable.</P>

Optimizing the Power Delivery Network in a Smartphone Platform

Woojoo Lee,Yanzhi Wang,Donghwa Shin,Chang, Naehyuck,Pedram, Massoud IEEE 2014 IEEE transactions on computer-aided design of inte Vol.33 No.1

<P>Smartphones consume a significant amount of power. Indeed, they can hardly provide a full day of use between charging operations even with a 2000 mAh battery. While power minimization and dynamic power management techniques have been heavily explored to improve the power efficiency of modules (processors, memory, display, GPS, etc.) inside a smartphone platform, there is one critical factor that is often overlooked: the power conversion efficiency of the power delivery network (PDN). This paper focuses on dc-dc converters, which play a pivotal role in the PDN of the smartphone platform. Starting from detailed models of the dc-dc converter designs, two optimization methods are presented: 1) static switch sizing to maximize the efficiency of a dc-dc converter under statistical loading profiles and 2) dynamic switch modulation to achieve the high efficiency enhancement under dynamically varying load conditions. To verify the efficacy of the optimization methods in actual smartphone platforms, this paper also presents a characterization procedure for the PDN. The procedure is as follows: 1) group the modules in the smartphone platform together and use profiling to estimate their average and peak power consumption levels and 2) build an equivalent dc-dc converter model for the power delivery path from the battery source to each group of modules and use linear regression to estimate the conversion efficiency of the corresponding equivalent converter. Experimental results demonstrate that the static switch sizing can achieve 6% power conversion efficiency enhancement, which translates to 19% reduction in power loss general usage of the smartphone. The dynamic switch modulation accomplishes similar improvement at the same condition, while also achieving high efficiency enhancement in various load conditions.</P>

Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems

Yanzhi Wang,Xue Lin,Younghyun Kim,Qing Xie,Pedram, Massoud,Naehyuck Chang IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.12

<P>In spite of extensive research it is still quite expensive to store electrical energy without converting it to a different form of energy. As of today, no single type of electrical energy storage (EES) element can fulfill all the desirable features of an ideal storage device, e.g., high-efficiency, high-power/energy capacity, low-cost, and long-cycle life. A hybrid EES system (HEES) consists of two or more heterogeneous EES elements, realizing the advantages of each EES element while hiding their weaknesses. HEES systems exhibit superior performance compared with homogeneous EES systems when appropriate charge allocation and replacement policies are developed and used. In addition, charge migration is mandatory because the optimal EES banks for charge allocation and replacement are in general different, and each EES bank has limited storage capacity. This paper formally describes the notion of charge migration efficiency and its optimization. We first define the charge migration architecture and the corresponding charge migration optimization problem. We provide a systematic solution for the single-source, single-destination charge migration problem considering the efficiency variation of the converters, the rate capacity and internal power loss of the storage element, the terminal voltage variation of the storage elements as a function of their state of charge, and so on. We also introduce the optimal solutions for both the time-constrained and -unconstrained versions of the charge migration problem formulations. Experimental results demonstrate significant charge migration efficiency improvement of up to 83.4%.</P>