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- 저자 : K.R. Padmavathi (검색결과 2 건)
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R. Ganesamoorthy,G. Suresh,K.R. Padmavathi,J. Rajaparthiban,R. Vezhavendhan,G. Bharathiraja 한국섬유공학회 2022 Fibers and polymers Vol.23 No.10
The influence of lignite flyash into the interpenetrating polymer network (IPN) matrix is thoroughly investigatedin this study. The standard weight ratio of E-Glass fiber have been chosen as the reinforcement into the IPN (vinylester/polyurethane) matrix, along with the varying loading of flyash as 0 %, 1 %, 3 %, 5 %, 7 %, 9 % (wt. ratio) respectively,fabricated through the hand lay-up technique. In order to completely understand the physical properties of the flyash loadedIPN composite (E-glass fiber reinforcement) specimen’s tests like differential thermal analysis (DTA), Tensile, Flexural,Compression, Impact, HDT (Heat Deflection Test), and wear test is performed. It was interesting to note that, upon loadingthe flyash into the matrix, the test result confirms that, there was a precipitous increase in the physical strength of all thespecimens’ up to the level of 5 % flyash loading except compressive and Barcoal hardness. Moreover to completely knowabout the bonding and de-bonding strength (flyash & matrix) of the fractured surfaces scanning electron microscope (SEM)analysis has been carried out. Out of all, the 5 % flyash loaded specimens have showed unique characteristics in physicalstrength, wear resistance and enhanced thermal stability as compared with the remaining set of flyash loaded samples.
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VLSI Implementation of Forward Error Control Technique for ATM Networks
G. Padmavathi,R. Amutha,S.K. Srivatsa 한국전자통신연구원 2005 ETRI Journal Vol.27 No.6
length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration(VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 × 5 matrix of data cells in a Virtex-EXCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.
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