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- 저자 : Jung Chak Ahn (검색결과 2 건)
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Hyuck In Kwon,박병국,In Man Kang,Jong Duk Lee,Jung Chak Ahn,Sang Sik Park,Woo Suk Hyun,Yong Hee Lee 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
High-field electrical stress effects on the mid-gap interface trap density (Dito) and the geometric mean capture cross sections (o) in n-MOSFETs have been studied using the pulsed interface probing (PIP) method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross-section values caused by the Fowler-Nordheim (F-N) electrical stress. A decrease in the mid-gap trap cross-sections following F-N tunneling injection is found. Our work also provides further insight into the in uence of electrical stress on mid-gap interface trap generation in n- MOSFETs without the assumption of a constant capture cross-section value during F-N stresses. High-field electrical stress effects on the mid-gap interface trap density (Dito) and the geometric mean capture cross sections (o) in n-MOSFETs have been studied using the pulsed interface probing (PIP) method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross-section values caused by the Fowler-Nordheim (F-N) electrical stress. A decrease in the mid-gap trap cross-sections following F-N tunneling injection is found. Our work also provides further insight into the in uence of electrical stress on mid-gap interface trap generation in n- MOSFETs without the assumption of a constant capture cross-section value during F-N stresses.
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Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon
In Man Kang,박병국,Hyuck In Kwon,Jong Duk Lee,Jung Chak Ahn,Myung Won Lee,Sang Sik Park,Yong Hee Lee 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at Ev + 0.16 eV, Ec ..0.23 eV, Ec ..0.55 eV, and Ev + 0.58 eV, respectively. The deep levels at Ec ..0.55 eV and Ev + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing. The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at Ev + 0.16 eV, Ec ..0.23 eV, Ec ..0.55 eV, and Ev + 0.58 eV, respectively. The deep levels at Ec ..0.55 eV and Ev + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing.
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