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Kim, Jonghoon J.,Heegon Kim,Jung, Daniel H.,Sumin Choi,Jaemin Lim,Youngwoo Kim,Junyong Park,Hyesoo Kim,Dongho Ha,Bae, Michael,Joungho Kim IEEE 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.4
<P>As the data rate of Low Power Double Data Rate 4 (LPDDR4) memory now exceeds 3.2 Gb/s, it is becoming more difficult to meet the target specifications. While testing has become of utmost importance, it is not viable to have a direct access to the signal pins in a package on package configuration due to the densely located array of solder balls; instead, a test interposer with an excellent electrical performance needs to be adopted to provide test access. In this paper, we first propose a novel test interposer scheme for testing LPDDR4 memory packages. For accurate testing without significant influence on the intrinsic signal path, the proposed test interposer is designed considering a number of signal integrity issues such as intersymbol interference, jitter, impedance matching, and crosstalk. Furthermore, by adopting silicone rubber sheet in place of soldering, the proposed test interposer enhances reusability of the packages with a fast setup time. Moreover, a reconstruction method is proposed that can reconstruct the voltage at application processor using the waveform captured on the test interposer, instead of probing at the ball gray array directly. Through a series of simulations and measurements, we experimentally verified the proposed test interposer. The proposed test interposer scheme can be widely adopted for testing of high-performance packages with its high accuracy and practicality.</P>
Kim, Jonghoon J.,Changhyun Cho,Bumhee Bae,Sukjin Kim,Sunkyu Kong,Heegon Kim,Jung, Daniel H.,Jiseong Kim,Joungho Kim IEEE 2014 IEEE transactions on components, packaging, and ma Vol.4 No.12
<P>A simultaneous switching current (SSC) drawn by an integrated circuit (IC) creates simultaneous switching noise on power nets, which in turn causes jitters in the I/O signals and reduces the maximum clock frequency. For a thorough analysis of high-speed ICs, there is a dire need to measure currents at specific power pins of the ICs. In this paper, a novel magnetically coupled embedded current probing structure is proposed for measuring the SSC on the chip level resulting from the logical activity of the I/O buffers. SSCs are found by capturing the magnetic flux induced by the SSC of interest, with the proposed embedded current probing structure using magnetic coupling, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of measurements with test vehicles fabricated on the chip level, we experimentally verified the proposed probing structures in the time and frequency domains and proved that they can effectively measure the SSC. Finally, future directions for improvements are discussed at the end of this paper.</P>
Jonghoon Kim,Hongseok Kim,In-Myoung Kim,Young-Il Kim,Seungyoung Ahn,Jiseong Kim,Joungho Kim 한국전자파학회JEES 2011 Journal of Electromagnetic Engineering and Science Vol.11 No.3
In this paper, we implemented and analyzed a wireless power transfer (WPT) system with a CSPR topology. CSPR refers to constant current source, series resonance circuit topology of a transmitting coil, parallel resonance circuit topology of a receiving coil, and pure resistive loading. The transmitting coil is coupled by a magnetic field to the receiving coil without wire. Although the electromotive force (emf) is small (about 4.5V), the voltage on load resistor is 148V, because a parallel resonance scheme was adopted for the receiving coil. The implemented WPT system is designed to be able to transfer up to 1 ㎾ power and can operate a LED TV. Before the implementation, the EMF reduction mechanism based on the use of ferrite and a metal shield box was confirmed by an EM simulation and we found that the EMF can be suppressed dramatically by using this shield. The operating frequency of the implemented WPT system is 30.7㎑ and the air gap between two coils is 150㎜. The power transferred to the load resistor is 147W and the real power transfer efficiency is 66.4 %.
30 Gbps High-Speed Characterization and Channel Performance of Coaxial Through Silicon Via
Jung, Daniel H.,Heegon Kim,Sukjin Kim,Kim, Jonghoon J.,Bumhee Bae,Jonghoon Kim,Jong-Min Yook,Jun-Chul Kim,Joungho Kim THE INSTITUTE OF ELECTRICAL ENGINEERS 2014 IEEE Microwave and Wireless Components Letters Vol. No.
<P>Coaxial through silicon via (TSV) technique allows reduction of high frequency loss due to conductivity in silicon substrate and flexibility in impedance by controlling the ratio of shield to center radii. For the first time, we measured and analyzed the high-speed channel performance of coaxial TSV. This letter presents the measurement results of the fabricated test vehicle in S-parameter and eye-diagram. The eye-diagram measurement results prove that coaxial TSV is capable of supporting signal transmission up to bit rate of 30 Gbps. The equivalent circuit model is suggested and experimentally verified by S-parameter comparison. Furthermore, the superiority of coaxial TSV over conventional TSV is confirmed by comparison of S-parameter results from equivalent circuit model simulation.</P>
Through-Silicon Via Capacitance–Voltage Hysteresis Modeling for 2.5-D and 3-D IC
Kim, Dong-Hyun,Kim, Youngwoo,Cho, Jonghyun,Bae, Bumhee,Park, Junyong,Lee, Hyunsuk,Lim, Jaemin,Kim, Jonghoon J.,Piersanti, Stefano,de Paulis, Francesco,Orlandi, Antonio,Kim, Joungho IEEE 2017 IEEE transactions on components, packaging, and ma Vol.7 No.6
<P>We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.</P>
Kim Eun-Kyung,Fenyi Justice Otoo,Kim Jae-Hee,Kim Myung-Hee,Yean Seo-Eun,Park Kye-Wol,Oh Kyungwon,윤성하,Ishikawa-Takata Kazuko,Park Jonghoon,Kim Jung Hyun,Yoon Jin-Sook 한국영양학회 2022 Nutrition Research and Practice Vol.16 No.5
BACKGROUND/OBJECTIVES The doubly labeled water (DLW) method is the gold standard for estimating total energy expenditure (TEE) and is also useful for verifying the validities of dietary evaluation tools. In this study, we compared the accuracy of total energy intakes (TEI) estimated by the 24-h diet recall method with TEE obtained using the doubly labeled water method. SUBJECTS/METHODS This study involved 71 subjects aged 20–49 yrs. Over a 14-day period, three 24-h diet recalls per subject (2 weekdays and 1 weekend day) were used to estimate energy intakes, while TEE was measured using the DLW method. The paired t-test was used to determine the significance of differences between TEI and TEE results, and the accuracy of the 24-h recall method was determined by accuracy predictions percentage, root mean square error, and bias. RESULTS Average study subject age was 33.4 ± 8.6 yrs. The association between TEI and TEE was positive and significant (r = 0.463, P < 0.001), and the difference between TEI (2,084.3 ± 684.2 kcal/day) and TEE (2,401.7 ± 480.3 kcal/day) was also significant (P < 0.001). In all study subjects, mean TEI was 12.0% (307.5 ± 629.3 kcal/day) less than mean TEE, and 12.2% (349.4 ± 632.5 kcal/day) less in men and 11.8% (266.7 ± 632.5 kcal/day) less in women. Rates of TEI underprediction for all study subjects, men, and women, were 60.5%, 51.4%, and 66.7%, respectively. CONCLUSIONS This study shows that 24-h diet recall underreports energy intakes. More research is needed to corroborate our findings and evaluate the accuracy of 24-h recall with respect to additional demographics.
Kim, Youngwoo,Cho, Jonghyun,Kim, Jonghoon J.,Cho, Kyungjun,Kim, Subin,Sitaraman, Srikrishna,Sundaram, Venky,Raj, Pulugurtha Markondeya,Tummala, Rao R.,Kim, Joungho [Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.3
<P>In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f(L) and f(U) of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below -40 dB) between f(L) of 5.8 GHz and f(U) of 9.6 GHz. Derived f(L) and f(U) based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.</P>
Coil Design and Shielding Methods for a Magnetic Resonant Wireless Power Transfer System
Jiseong Kim,Jonghoon Kim,Sunkyu Kong,Hongseok Kim,In-Soo Suh,Nam Pyo Suh,Dong-Ho Cho,Joungho Kim,Seungyoung Ahn IEEE 2013 Proceedings of the IEEE Vol.101 No.6
<P>In this paper, we introduce the basic principles of wireless power transfer using magnetic field resonance and describe techniques for the design of a resonant magnetic coil, the formation of a magnetic field distribution, and electromagnetic field (EMF) noise suppression methods. The experimental results of wireless power transfer systems in consumer electronics applications are discussed in terms of issues related to their efficiency and EMF noise. Furthermore, we present a passive shielding method and a magnetic field cancellation method using a reactive resonant current loop and the utilization of these methods in an online electric vehicle (OLEV) system, in which an OLEV green transportation bus system absorbs wireless power from power cables underneath the road surface with only a minimal battery capacity.</P>
김종훈(Jonghoon Kim),김근일(Guenil Kim),김은호(Eunho Kim) 대한기계학회 2021 대한기계학회 춘추학술대회 Vol.2021 No.6
탄소섬유 복합재료(CFRP)는 높은 비 강성과 비 강도 뿐만 아니라 높은 성형성과 내열성 등 다양한 장점을 갖고 있어 다양한 산업분야에서 활용이 확대되고 있다. 하지만 충격으로 인해 층간 분리와 같은 표면에 드러나지 않는 내부 손상(BVID)이 발생하기 쉬우며 이를 위해 복합재료의 내부결함을 탐지하는 비파괴검사기법이 활발히 연구되고 있다. 본 연구에서는 입자 체인(Granular chain)에서의 비선형 고립파를 이용하여 측정부위에서 떨어진 복합재료의 결함 유무를 판별하기 위한 선행연구로 복합재료 실린더에서의 탄성파 전파 거동을 측정하였다. 비선형 고립파가 복합재료 실린더에 입사되면 복합재료 표면을 따라 전파되는데, 이때 표면을 따라 전파되는 탄성파가 복합재료 실린더의 손상 부위에서 산란되면 산란된 탄성파는 다시 입자센서에 영향을 미치게 된다. 이러한 미소 산란파가 입자 센서에 미치는 영향을 파악하기 위해서는 먼저 복합재료 실린더에서 탄성파의 산란 거동을 파악할 필요가 있다. 본 연구에서는 실험적으로 비선형 고립파가 실린더에 입사 되었을 때, 복합재료 실린더를 통해서 전파되는 탄성파를 측정하였다. 작은 크기로 빠르게 전파되는 탄성파를 측정하기 위해 정밀한 레이져 센서(Laser Doppler Vibrometry)를 이용하였다. 등 간격의 20x9 격자를 실린더 표면에 표시하고 각 위치에서 속도를 측정한 후 동기화 시켜 탄성파의 전파 거동을 가시화하였다. 충격 손상이 있는 쪽 면과 없는 쪽 면에서의 탄성파를 각각 측정하여 비교한 결과 복합재료의 충격 손상 위치에서 탄성파가 산란(scattering)되는 현상을 파악하였으며, 산란된 탄성파가 입자센서에 미치는 영향을 함께 확인하였다. 본 연구 결과를 기반으로 향후 입자센서의 신호 특성을 이용하여 복합재료 실린더의 손상을 검출하는 연구를 진행하고자 한다. [그림 본문 참조]