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Han, Kwangseok,Gil, J.,Song, Seong-Sik,Han, Jeonghu,Shin, Hyungcheol,Kim, Choong-Ki,Lee, Kwyro IEEE 2005 IEEE journal of solid-state circuits Vol.40 No.3
Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF<SUB>50</SUB> and NF<SUB>min</SUB> are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs.
Extraction of Substrate Resistances of RF MOSFETs with Various Geometries
Han Jeonghu 한국물리학회 2003 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.42 No.III
This paper proposes a simple and accurate method for extracting the substrate resistance of an RF Metal-oxide-semiconductor field-effect-transistor (MOSFET) from the measured network parameters. The extraction results for 0.18-m nMOSFETs are presented for various bias conditions and various geometries. The extracted results are veried by using the parameter for MOSFET macro-modeling.
Han, Jeonghu,Kim, Younsuk,Park, Changkun,Lee, Dongho,Hong, Songcheol JOHN WILEY & SONS LTD 2007 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.49 No.6
<P>A 900-MHz linear power amplifier with an adaptive bias scheme is fabricated using a 0.25-μm CMOS technology. The power amplifier operates over the range of 860–960 MHz, which is the ultrahigh-frequency band for radio frequency identification (RFID). All matching networks and RF chokes are implemented on a chip. The developed power amplifier provides a 1-dB-gain-compression point (P<SUB>1 dB</SUB>) of 27 dBm and a power-added-efficiency (PAE) of 28% at the P<SUB>1 dB</SUB>. The adaptive bias scheme enables the power amplifier to reduce the quiescent power consumption from 280 to 80 mW by adjusting the gate voltage of power transistors as a function of the input power. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1241–1245, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22435</P>
A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers
Ockgoo Lee,Jeonghu Han,Kyu Hwan An,Dong Ho Lee,Kun-Seok Lee,Songcheol Hong,Chang-Ho Lee IEEE 2010 IEEE journal of solid-state circuits Vol.45 No.10
<P>A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.</P>
CMOS power cell with improved junction breakdown using interdigitated body contact
Park, Changkun,Han, Jeonghu,Hong, Songcheol Wiley Subscription Services, Inc., A Wiley Company 2007 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.49 No.12
<P>A power-cell for RF power applications is designed using 0.35-μm standard CMOS technology. An interdigitated body contact method is proposed and applied to a RF power-cell. A total gate width of the designed power-cell is 3.2 mm. The proposed RF power-cell has a higher junction breakdown voltage than that of a conventional RF power-cell. The breakdown voltage of the proposed CMOS power-cell at zero gate voltage was found to be ∼8 V. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 3085–3087, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22908</P>
Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier
Changkun Park,Dong Ho Lee,Jeonghu Han,Songcheol Hong Professional Technical Group on Microwace Theory a 2007 IEEE transactions on microwave theory and techniqu Vol.55 No.10
<P>A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.</P>