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3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability
Jaeil Lim,Hyunyul Lim,Sungho Kang IEEE 2015 IEEE transactions on computer-aided design of inte Vol.34 No.9
<P>The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.</P>
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests
Park, Jaeseok,Lim, Hyunyul,Kang, Sungho IEEE 2017 IEEE transactions on computer-aided design of inte Vol.36 No.2
<P>Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [ fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.</P>
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories
Wooheon Kang,Changwook Lee,Hyunyul Lim,Sungho Kang Institute of Electrical and Electronics Engineers 2015 IEEE transactions on reliability Vol. No.
<P>A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.</P>