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A Wideband On-Interposer Passive Equalizer Design for Chip-to-Chip 30-Gb/s Serial Data Transmission
Heegon Kim,Jonghyun Cho,Joohee Kim,Sumin Choi,Kiyeong Kim,Junho Lee,Kunwoo Park,Pak, Jun So,Joungho Kim IEEE 2015 IEEE transactions on components, packaging, and ma Vol.5 No.1
<P>In this paper, a novel on-interposer passive equalizer is proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the on-interposer shunt metal lines to produce the high-pass filter. This filter enables the proposed equalizer to exhibit wideband channel equalization and low power-consumption. Based on the equivalent-circuit model of the proposed on-interposer passive equalizer, the physical dimensions of the equalizer are optimized for 30-Gb/s serial data transmission. The performance of the proposed equalizer with the optimized dimensions was successfully demonstrated by both frequency- and time-domain measurements at data rates of up to 30 Gb/s. In addition, a compact on-interposer passive equalizer was designed for the wide I/O interposer using the same mechanism. The improved quality of serial data transmission in the equalized wide I/O on-interposer channel was successfully verified by simulations at data rates of up to 10 Gb/s.</P>
Kim, Jonghoon J.,Changhyun Cho,Bumhee Bae,Sukjin Kim,Sunkyu Kong,Heegon Kim,Jung, Daniel H.,Jiseong Kim,Joungho Kim IEEE 2014 IEEE transactions on components, packaging, and ma Vol.4 No.12
<P>A simultaneous switching current (SSC) drawn by an integrated circuit (IC) creates simultaneous switching noise on power nets, which in turn causes jitters in the I/O signals and reduces the maximum clock frequency. For a thorough analysis of high-speed ICs, there is a dire need to measure currents at specific power pins of the ICs. In this paper, a novel magnetically coupled embedded current probing structure is proposed for measuring the SSC on the chip level resulting from the logical activity of the I/O buffers. SSCs are found by capturing the magnetic flux induced by the SSC of interest, with the proposed embedded current probing structure using magnetic coupling, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of measurements with test vehicles fabricated on the chip level, we experimentally verified the proposed probing structures in the time and frequency domains and proved that they can effectively measure the SSC. Finally, future directions for improvements are discussed at the end of this paper.</P>
Kim, Jonghoon J.,Heegon Kim,Jung, Daniel H.,Sumin Choi,Jaemin Lim,Youngwoo Kim,Junyong Park,Hyesoo Kim,Dongho Ha,Bae, Michael,Joungho Kim IEEE 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.4
<P>As the data rate of Low Power Double Data Rate 4 (LPDDR4) memory now exceeds 3.2 Gb/s, it is becoming more difficult to meet the target specifications. While testing has become of utmost importance, it is not viable to have a direct access to the signal pins in a package on package configuration due to the densely located array of solder balls; instead, a test interposer with an excellent electrical performance needs to be adopted to provide test access. In this paper, we first propose a novel test interposer scheme for testing LPDDR4 memory packages. For accurate testing without significant influence on the intrinsic signal path, the proposed test interposer is designed considering a number of signal integrity issues such as intersymbol interference, jitter, impedance matching, and crosstalk. Furthermore, by adopting silicone rubber sheet in place of soldering, the proposed test interposer enhances reusability of the packages with a fast setup time. Moreover, a reconstruction method is proposed that can reconstruct the voltage at application processor using the waveform captured on the test interposer, instead of probing at the ball gray array directly. Through a series of simulations and measurements, we experimentally verified the proposed test interposer. The proposed test interposer scheme can be widely adopted for testing of high-performance packages with its high accuracy and practicality.</P>
30 Gbps High-Speed Characterization and Channel Performance of Coaxial Through Silicon Via
Jung, Daniel H.,Heegon Kim,Sukjin Kim,Kim, Jonghoon J.,Bumhee Bae,Jonghoon Kim,Jong-Min Yook,Jun-Chul Kim,Joungho Kim THE INSTITUTE OF ELECTRICAL ENGINEERS 2014 IEEE Microwave and Wireless Components Letters Vol. No.
<P>Coaxial through silicon via (TSV) technique allows reduction of high frequency loss due to conductivity in silicon substrate and flexibility in impedance by controlling the ratio of shield to center radii. For the first time, we measured and analyzed the high-speed channel performance of coaxial TSV. This letter presents the measurement results of the fabricated test vehicle in S-parameter and eye-diagram. The eye-diagram measurement results prove that coaxial TSV is capable of supporting signal transmission up to bit rate of 30 Gbps. The equivalent circuit model is suggested and experimentally verified by S-parameter comparison. Furthermore, the superiority of coaxial TSV over conventional TSV is confirmed by comparison of S-parameter results from equivalent circuit model simulation.</P>
Parallelizing H.264 and AES Collectively
( Heegon Kim ),( Sungju Lee ),( Yongwha Chung ),( Sung Bum Pan ) 한국인터넷정보학회 2013 KSII Transactions on Internet and Information Syst Vol.7 No.9
Many applications can be parallelized by using multicore platforms. We propose a load-balancing technique for parallelizing a whole application, whose first module (H.264) has data independency and whose second module (AES) has data dependency. Instead of distributing the first module symmetrically over the multi-core platform, we distribute the data-independent workload asymmetrically in order to start the data-dependent workload as early as possible. Based on the experimental results with a compression/encryption application, we confirm that the asymmetric load balancing can provide better performance than the typical symmetric load balancing.