http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
A sub-0.5 V operating RF low noise amplifier using tunneling-FET
Jhon, Hee-Sauk,Jeon, Jongwook,Kang, Myunggon,Choi, Woo Young Institute of Pure and Applied Physics 2017 Japanese Journal of Applied Physics Vol. No.
<P>60 nm tunneling FET (TFET) based low noise amplifier (LNA) with a sub-0.5 V supply voltage for 2.4GHz WSN application has been evaluated systematically from device level up to circuit level design. With the help of TFET's unique property of high subthreshold swing, it shows that substantial increase of gain performance was confirmed compared to that of conventional LNA using 60nm bulk MOSFET at ultra-low voltage (ULV) condition. From the simulation study, TFET LNA at 0.4 V operating voltage has the gain of 15.1 dB and noise figure 50 of 3.5 dB while dissipating DC power consumption of 0.41 mW. (C) 2017 The Japan Society of Applied Physics</P>
Hee-Sauk Jhon,Jae-Hong Lee,Jaeho Lee,Byoungchan Oh,Ickhyun Song,Yeonam Yun,Byung-Gook Park,Jong-Duk Lee,Hyungcheol Shin IEEE 2009 IEEE electron device letters Vol.30 No.12
<P>In this letter, <I>f</I> <SUB>max</SUB> improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. We confirmed that the circuit-level MOS transistor has a tradeoff among the extrinsic capacitive and resistive parasitics (<I>C</I> <SUB>gd</SUB>, <I>C</I> <SUB>gs</SUB>, and <I>Rg</I>) on circular gate metal layers. Furthermore, it reduces the extrinsic <I>C</I> <SUB>gd</SUB> and <I>Rg,</I> which have great effect on the RF performance, simultaneously. For qualitative analysis of the capacitive coupling, which attributed to undesired extrinsic capacitance, capacitive coupling paths were separately defined as two cases, namely, direct capacitive coupling and indirect capacitive coupling. Some of the key small-signal parameters were also extracted and compared with different types of transistors, and they show a good match with the observed trends. The proposed layout exhibits the improvement of <I>f</I> <SUB>max</SUB> up to ~ 21% without <I>fT</I> variation compared to a reference device due to reduced extrinsic <I>Rg</I> and <I>C</I> <SUB>gd</SUB> parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.</P>
Jhon, Hee-Sauk,Jung, Hakchul,Koo, Minsuk,Song, Ickhyun,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.51 No.5
<P>A low supply voltage and highly linear subthreshold CMOS low noise amplifier (LNA) for 2.4 GHz wireless sensor network applications is presented in this letter. We applied multiple gated transistor (MGTR) technique in subthreshold region to compensate the linearity degradation of low supply cascode topology. Moreover, the feedback capacitor, C<SUB>f</SUB> is used to enhance the power gain of amplifier without additional dc-power dissipation. The proposed LNA has gain of 13.1 dB, noise figure (NF) of 3.8 dB, and −2.5 dBm IIP3 while dissipating only 0.49 mW from 0.7 V supply. The LNA has been designed using a 0.13 μm 1P8M standard CMOS process with top metal thickness of 3.3 μm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1316–1320, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24333</P>
2.4 GHz ISM-Band Receiver Design in a 0.18 <tex> $\mu{\hbox{m}}$</tex> Mixed Signal CMOS Process
Hee-Sauk Jhon,Ickhyun Song,In Man Kang,Hyungcheol Shin IEEE 2007 IEEE microwave and wireless components letters Vol.17 No.10
<P>This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm<SUP>2</SUP>.</P>
Low power size-efficient CMOS UWB low-noise amplifier design
Jhon, Hee-Sauk,Song, Ickhyun,Jeon, Jongwook,Koo, MinSuk,Park, Byung-Gook,Lee, Jong Duk,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.51 No.2
<P>The design and measurement results of 3–5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the transconductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascode structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 3.3–4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input P1dB and input IP3 (IIP3) at 4 GHz are about −6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 494–496, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24104</P>
Size efficient low-noise amplifier for 2.4 GHz ISM-band transceiver
Jhon, Hee-Sauk,Jung, Hakchul,Jeon, Jongwook,Koo, MinSuk,Park, Byung-Gook,Lee, Jong Duk,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.51 No.10
<P>This letter presents the implementation technique to reduce circuit area in designing 2.4 GHz CMOS low-noise amplifier (LNA) using size efficient inductors. We applied a vertically shunt (M6/M5) and a 3-D helical inductor to input and output matching network to obtain low noise figure and to save silicon area, simultaneously. Because these inductors have smaller area occupation, overall Si area was reduced. Moreover, the feedback capacitor, C<SUB>f</SUB> is used to compensate the gain degradation from the high resistive 3-D helical inductor at the LNA output stage. The proposed LNA has a gain of 12.5 dB, noise figure (NF) of 2.72 dB, and −5 dBm IIP3, whereas dissipating 5.3 mA from 1.5 V supply. Without any degradation in terms of circuit performance, the size of proposed LNA is reduced by 49.5% compared with that using the conventional asymmetric inductors. For low cost, the LNA has been fabricated using a 0.18 μm mixed-signal CMOS process with top metal thickness of 0.84 μm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2304–2308, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24600</P>
Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors
전희석(Hee-Sauk Jhon),송익현(Ickhyun Song),윤여남(Yeonam Yun),구민석(Minsuk Koo),정학철(Hakchul Jung),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using size efficient inductors. We applied vertical shunt symmetric and helical inductor to match the input and output in 2.4 ㎓ CMOS LNA to reduce the circuit area. In this paper, the case of conventional LNA using asymmetric inductor, and that of ones using vertical shunt symmetrical and helical inductor with a relatively higher number of turns have been compared in order to present a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.
Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET
Jeon, Jongwook,Jhon, Hee-Sauk,Kang, Myounggon Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.12
<P>The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.</P>
Bias and Device Optimization for 0.13-㎛ CMOS Low-Noise Amplifier Design
Ickhyun Song,Hakchul Jung,Hee Sauk Jhon,Hyungcheol Shin 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A design approach for optimizing the performance of low-noise amplifiers is introduced. Figure of merit of LNAs which is composed of signal power gain, noise factor, and power consumption is used for evaluating the overall performance. Each factor is anayltically expressed in device parametes. By using this method, FoM of LNAs are maximized prior to the fabrication of circuits.