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Bae, Hagyoul,Bang, Tewook,Kim, Choong-Ki,Hur, Jae,Kim, Seyeob,Jeon, Chang-Hoon,Park, Jun-Young,Ahn, Dae-Chul,Kim, Gun-Hee,Son, Yunik American Scientific Publishers 2017 Journal of Nanoscience and Nanotechnology Vol.17 No.5
<P>We report an accurate extraction technique of effective mobility (mu(eff)) by considering gate-bias (V-GS) dependent effective inversion charges (Q(inv,eff)) as a normalized correction factor (sigma(V-GS)) when using the gate-to-source/drain capacitance-voltage (C-V) measurement in a p-channel Si/SiGe MOSFET with a floating body structure. In the proposed technique, two different capacitance-voltage configurations: a gate-to-source/drain (CG-SD) configuration without body contact and a gate-to-source/drain/body (CG-SDB) configuration with body contact are utilized for the accurate extraction of mu(eff).</P>
Hagyoul Bae,Seok Cheon Baek,Sunyeong Lee,Jaeman Jang,Ja Sun Shin,Daeyoun Yun,Hyojong Kim,Dae Hwan Kim,Dong Myong Kim IEEE 2010 IEEE electron device letters Vol.31 No.11
<P>The separate extraction of asymmetric source (<I>R</I><SUB>S</SUB>) and drain (<I>R</I><SUB>D</SUB>) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple “parasitic junction current method” (PJCM) for the separate extraction of <I>R</I><SUB>S</SUB>, <I>R</I><SUB>D</SUB>, and <I>R</I><SUB>SUB</SUB> (substrate resistance) in MOSFETs. We applied the proposed PJCM to n-channel MOSFETs with different <I>W</I>/<I>L</I> combinations and verified its usefulness in the robust extraction of <I>R</I><SUB>S</SUB>, <I>R</I><SUB>D</SUB>, and <I>R</I><SUB>SUB</SUB>.</P>
Hagyoul Bae,Sungchul Kim,Minkyung Bae,Ja Sun Shin,Dongsik Kong,Hyunkwang Jung,Jaeman Jang,Jieun Lee,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.6
<P>Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., <I>RS</I> and <I>RD</I>, respectively, from the total resistance <I>R</I><SUB>TOT</SUB> is very important in the design, modeling, and characterization of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Due to the insulated gate structure, however, separate extraction is difficult through direct-current <I>I</I>-<I>V</I> characterization. In this letter, we propose a simple and useful technique for separate extraction of <I>RS</I> from <I>RD</I> in a-IGZO TFTs through a two-terminal parallel-mode <I>C</I> -<I>V</I> technique. We experimentally verified the validity of the proposed technique by comparing the result with the source-to-drain resistance from the <I>I</I>-<I>V</I> characteristics.</P>
Bae, Hagyoul,Noh, Jinhyun,Alghamdi, Sami,Si, Mengwei,Ye, Peide D. IEEE 2018 IEEE electron device letters Vol.39 No.11
<P>A novel technique is proposed for the simultaneous extraction of energy distribution of donor- and acceptor-like interface trap states [ <TEX>${D}_{\text {it}\_{}{D}}$</TEX>( <TEX>${E}$</TEX>) and <TEX>${D}_{\text {it}\_{}{A}}$</TEX> ( <TEX>${E}$</TEX>)] over a wide range of bandgap energy using deep UV light with sub-bandgap ( <TEX>${E}_{\text {ph}}={h}\nu < {E}_{g}$</TEX>) photons less than the bandgap of the <TEX>$\beta$</TEX>-gallium oxide ( <TEX>$\beta$</TEX>-Ga<SUB>2</SUB>O<SUB>3</SUB>) channel material in the <TEX>$\beta$</TEX>-Ga<SUB>2</SUB>O<SUB>3</SUB> field-effect transistors. In the proposed technique, we characterized <TEX>${D}_{\text {it}\_{}{D}}$</TEX>( <TEX>${E}$</TEX>) and <TEX>${D}_{\text {it}\_{}{A}}$</TEX>( <TEX>${E}$</TEX>) separately based on the difference in the gate voltage ( <TEX>${V} _{\text {GS}}$</TEX>)-dependent ideality factors [ <TEX>${d} \Delta \eta$</TEX>( <TEX>${V} _{\text {GS}}$</TEX>)/ <TEX>$dV_{\text {GS}}$</TEX>] for the photoresponsive carriers excited from <TEX>${D} _{\text {it}\_{}{D}}$</TEX>(E) and <TEX>${D} _{\text {it}\_{}{A}}$</TEX>( <TEX>${E}$</TEX>) under two different regions ( <TEX>${V} _{\text {ON}}< {V}_{\text {GS}}< {V}_{\text {FB}}$</TEX> and <TEX>${V} _{\text {FB}}< {V}_{\text {GS}}< {V}_{T}$</TEX>) in the subthreshold operation.</P>
Hagyoul Bae,Hyunjun Choi,Sungwoo Jun,Chunhyung Jo,Yun Hyeok Kim,Jun Seok Hwang,Jaeyeop Ahn,Oh, Saeroonter,Jong-Uk Bae,Sung-Jin Choi,Dae Hwan Kim,Dong Myong Kim IEEE 2013 IEEE electron device letters Vol.34 No.12
<P>We report a novel technique for simultaneous extraction of subgap donor- and acceptor-like density of states [g<SUB>D</SUB>(E) and g<SUB>A</SUB>(E)] over the subgap energy range (E<SUB>V</SUB> <;E<;E<SUB>C</SUB>) using a single-scan monochromatic photonic capacitance-voltage technique in n-channel amorphous indium-gallium-zinc-oxide thin-film transistors. In the proposed technique, we applied two different equivalent circuit models for the photoresponsive carriers excited from g<SUB>D</SUB>(E) and g<SUB>A</SUB>(E) under depletion (V<SUB>GS</SUB> <; V<SUB>FB</SUB>) and accumulation (V<SUB>GS</SUB> <; V<SUB>FB</SUB>) bias by employing a sub-bandgap optical source that includes a relation between photon energy (E<SUB>ph</SUB>) and bandgap energy (E<SUB>g</SUB>) as h<SUB>v</SUB> = E<SUB>ph</SUB> <; E<SUB>g</SUB>.</P>
Hagyoul Bae,Sungwoo Jun,Choon Hyeong Jo,Hyunjun Choi,Jaewook Lee,Yun Hyeok Kim,Seonwook Hwang,Hyun Kwang Jeong,Inseok Hur,Woojoon Kim,Daeyoun Yun,Euiyeon Hong,Hyojoon Seo,Dae Hwan Kim,Dong Myong Kim IEEE 2012 IEEE electron device letters Vol.33 No.8
<P>We propose a modified conductance method for extraction of the subgap density of states (DOS) in amorphous indium-gallium-zinc oxide thin-film transistors by using the measured capacitance and conductance through the capacitance-voltage (C-V) measurement. In the proposed method, the subgap DOS [g<SUB>A</SUB>(E)] is extracted from the frequency-dispersive C-V characteristics by localized traps in the active channel region. The extracted g<SUB>A</SUB>(E) shows a superposition of the exponential tail states and the exponential deep states over the bandgap (N<SUB>TA</SUB> = 3 × 10<SUP>18</SUP> cm<SUP>-3</SUP> · eV<SUB>-1</SUB>, N<SUB>DA</SUB> = 2.8 × 10<SUP>17</SUP> cm<SUP>-3</SUP> · eV-1, kT<SUB>TA</SUB> = 0.04 eV, and kT<SUB>DA</SUB> = 0.77 eV). We note that the gate-bias-dependent Cfree by free electron charges can be separated from C<SUB>loc</SUB> by localized trap charges through the proposed method.</P>
Hagyoul Bae,Jaeman Jang,Ja Sun Shin,Daeyoun Yun,Jieun Lee,Tae Wan Kim,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.6
<P>A new technique for a separate extraction of the current-path-dependent resistance (R<SUB>SD0</SUB>) from the contact-dependent source and drain resistances (R<SUB>Se</SUB> and R<SUB>De</SUB>) is reported for a single MOSFET. We also report a technique for a separation of V<SUB>GS</SUB>-dependent source and drain resistance (R<SUB>SDi</SUB>) from the V<SUB>GS</SUB>- and L<SUB>eff</SUB>-dependent channel resistance (R<SUB>ch</SUB>) with multiple MOSFETs. We confirm the proposed techniques applied to n-channel MOSFETs with various W/L combinations and obtain R<SUB>Se</SUB> = 10.5 - 12.4 Ω , R<SUB>De</SUB> ≅ 12.7 Ω, and R<SUB>SD0</SUB> = 4.7 Ω for W = 10 μm. V<SUB>GS</SUB>-dependent but L-independent R<SUB>SDi</SUB> is extracted to be 2.8 - 4.2 Ω.</P>
Bae, Hagyoul,Jun, Sungwoo,Kim, Choong-Ki,Ju, Byeong-Kwon,Choi, Yang-Kyu IOP 2018 Journal of Physics. D, Applied Physics Vol.51 No.10
<P>Few-layer molybdenum disulfide (MoS<SUB>2</SUB>) has attracted a great deal of attention as a semiconductor material for electronic and optoelectronic devices. However, the presence of localized states inside the bandgap is a critical issue that must be addressed to improve the applicability of MoS<SUB>2</SUB> technology. In this work, we investigated the density of states (DOS: <I>g</I>(<I>E</I>)) inside the bandgap of MoS<SUB>2</SUB> FET by using a current–voltage (<I>I</I>–<I>V</I>) analysis technique with the aid of high vacuum annealing (HVA). The <I>g</I>(<I>E</I>) can be obtained by combining the trap density and surface potential (<I>ψ</I> <SUB>S</SUB>) extracted from a consistent subthreshold current (<I>I</I> <SUB>D-sub</SUB>). The electrical performance of MoS<SUB>2</SUB> FETs is strongly dependent on the inherent defects, which are closely related to the <I>g</I>(<I>E</I>) in the MoS<SUB>2</SUB> active layer. By applying the proposed technique to the MoS<SUB>2</SUB> FETs, we were able to successfully characterize the <I>g</I>(<I>E</I>) after stabilization of the traps by the HVA, which reduces the hysteresis distorting the intrinsic <I>g</I>(<I>E</I>). Also, the change of sulfur ions in MoS<SUB>2</SUB> film before and after the HVA treatment is investigated directly by Auger electron spectroscopy analysis. The proposed technique provides a new methodology for active channel engineering of 2D channel based FETs such as MoS<SUB>2</SUB>, MoTe<SUB>2</SUB>, WSe<SUB>2</SUB>, and WS<SUB>2</SUB>.</P>
Hagyoul Bae,Inseok Hur,Ja Sun Shin,Daeyoun Yun,Euiyoun Hong,Keum-Dong Jung,Mun-Soo Park,Sunwoong Choi,Won Hee Lee,Mihee Uhm,Dae Hwan Kim,Dong Myong Kim IEEE 2012 IEEE electron device letters Vol.33 No.4
<P>We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances (<I>RS</I> and <I>RD</I>) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, <I>C</I>- <I>V</I> and <I>I</I> -<I>V</I> measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness <I>T</I><SUB>IGZO</SUB> , the gate length <I>L</I>, and the overlap length <I>L</I><SUB>ov</SUB> between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component <I>RH</I> considering the transfer resistance <I>R</I><SUB>LT</SUB> depending on the transfer length <I>LT</I> and the channel resistance <I>R</I><SUB>CH</SUB>, as well as the vertical components in the S/D <I>R</I><SUB>VS</SUB> and <I>R</I><SUB>VD</SUB>. We confirmed the proposed technique through a separate extraction of <I>VGS</I> -independent contact resistances (<I>R</I><SUB>CS</SUB>, <I>R</I><SUB>CD</SUB>) from the channel length- and <I>VGS</I>-dependent <I>R</I><SUB>LT</SUB> and <I>R</I><SUB>CH</SUB>.</P>
Bae, Hagyoul,Jang, Byung Chul,Park, Hongkeun,Jung, Soo-Ho,Lee, Hye Moon,Park, Jun-Young,Jeon, Seung-Bae,Son, Gyeongho,Tcho, Il-Woong,Yu, Kyoungsik,Im, Sung Gap,Choi, Sung-Yool,Choi, Yang-Kyu American Chemical Society 2017 NANO LETTERS Vol.17 No.10
<P>Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.</P>