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Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS
Kosuke Furuichi,Hiromu Uemura,Natsuyuki Koda,Hiromi Inaba,Keiji Kishine 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper describes a method of designing a circuit to detect high-linearity delay at 10 Gb/s. We proposed a transmission system for additional data in previous work, by using a frequency modulation technique. The demodulation characteristics in the receiver strongly depended on data speed. As the data speed gets higher, demodulation characteristics linearity degradation become larger. In this paper, we propose a circuit to provide high-linearity demodulation characteristics by using an emphasis technique which reduces degradation in the demodulated signal. We fabricated the circuit to detect delay with an emphasis technique by using 65- nm CMOS process. The results we obtained from measurements, revealed an integrated circuit (IC) achieved 10% higher linearity than a receiver without emphasis at 10 Gb/s.
Natsuyuki Koda,Furuichi Kosuke,Hiromu Uemura,Hiromi Inaba,Keiji Kishine 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper proposes a simple and low power highly sensitive frequency demodulator. In the previous work, we proposed a multiplex communication system that transmits additional data by using a frequency modulation technique and the proposed circuit provided highly sensitive characteristics on frequency demodulation. However, with this configuration, there is the problem that the power consumption and the number of control points increase. Therefore, in this paper, we propose a simple and lower power circuit configuration. We investigated the characteristics of these frequency demodulators using a prototype demodulation system consisting of an FPGA and discrete devices. Compared with the delay detection circuit, the proposed simple and lower power demodulation system, which showed the same output characteristics as the conventional sensitive demodulator, successfully detected about twice the detection data than the delay detection circuit did.
10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS
Hiromu Uemura,Kosuke Furuichi,Natsuyuki Koda,Hiromi Inaba,Keiji Kishine 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2
Currently, there is a great demand for high speed and large capacity communication systems. Therefore, it is important to develop circuit and device technologies that support these systems. Furthermore, it is important that high speed and large capacity systems are developed based on those technologies. In this paper, we propose a transmitter design method for the transmission system that the additional signal add to 10-Gb/s signal. The system transmits the data frames and the additional information simultaneously. To add the additional information, called the "labeling signal", to the data frames, we perform a frequency modulation technique on the transmitted data frames. To confirm the performance of the proposed circuit and design method, we fabricate an IC with the proposed system’s transmitter by using the 65-nm CMOS process. We confirm that the data frames are frequency modulated and the transmitter generates the frequency-modulated data frames.