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Neuromorphic Vision Hybrid RRAM-CMOS Architecture
Eshraghian, Jason Kamran,Cho, Kyoungrok,Zheng, Ciyan,Nam, Minho,Iu, Herbert Ho-Ching,Lei, Wen,Eshraghian, Kamran IEEE 2018 IEEE transactions on very large scale integration Vol.26 No.12
<P>The development of a bioinspired image sensor, which can match the functionality of the vertebrate retina, has provided new opportunities for vision systems and processing through the realization of new architectures. Research in both retinal cellular systems and nanodriven memristive technology has made a challenging arena more accessible to emulate features of the retina that are closer to biological systems. This paper synthesizes the signal flow path of photocurrent throughout a retina in a scalable 180-nm CMOS technology, which initiates at a <TEX>$128\times 128$</TEX> active pixel image sensor, and converges to a <TEX>$16\times 16$</TEX> array, where each node emits a spike train synonymous to the function of the retinal ganglionic output cell. This signal can be sent to the visual cortex for image interpretation as part of an artificial vision system. Layers of memristive networks are used to emulate the functions of horizontal and amacrine cells in the retina, which average and converge signals. The resulting image matches biologically verified results within an error margin of 6% and exhibits the following features of the retina: lateral inhibition, asynchronous adaptation, and a low-dynamic-range integration active pixel sensor to perceive a high-dynamic-range scene.</P>
Maximization of Crossbar Array Memory Using Fundamental Memristor Theory
Eshraghian, Jason K.,Cho, Kyoung-Rok,Iu, Herbert H. C.,Fernando, Tyrone,Iannella, Nicolangelo,Kang, Sung-Mo,Eshraghian, Kamran IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.12
<P>The packing density associated with crossbar arrays offers important architectural solutions to numerous forms of computational engines. Mitigation of sneak paths in the crossbar array, however, requires additional layers in fabrication technology to impede current flow in order to avoid undesired changes to the state when reading and writing to and from the array. This results in an unavoidable increase in the vertical stacking dimension of the array. With the recent emergence of bistable memristors under both dc and ac, by adopting their asymptotic dynamics, we realize a significant improvement in memory construct and spatial constraints of memristor crossbar arrays. In this brief, we formalize a method of configuring a whole array architecture to any permutation of states without sacrificing array density by using a rigorous theoretical analysis, and confirmed via simulation.</P>
Eshraghian, Kamran,Cho, Kyoung-Rok The Korean Institute of Electrical and Electronic 2010 Transactions on Electrical and Electronic Material Vol.11 No.3
The convergence of significantly different and disparate technologies such as spintronics, carbon nano tube field effect transistors, photon and bio-responsive molecular switches, memristor and memristive systems and metamaterials, coupled with energy scavenging sources are gaining a renewed focus in the quest for new products. This paper will provide an insight into an anticipated technological revolution and will highlight a futuristic Roadmap to capture opportunities that are brought about as the results of formulation of new circuit components basically driven by emergence of nanoscale materials as part of System on System integration. Challenges as the result of new lumped components such as memristor, metamaterial-based lumped components and the like that will challenge the designers' comfort zone will also be discussed.
Eshraghian, Kamran The Korean Institute of Electrical and Electronic 2010 Transactions on Electrical and Electronic Material Vol.11 No.6
The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.
Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation
Eshraghian, K.,Kavehei, O.,Kyoung-Rok Cho,Chappell, J. M.,Iqbal, A.,Al-Sarawi, S. F.,Abbott, D. IEEE 2012 Proceedings of the Institute of Electrical and Ele Vol.100 No.6
<P>The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.</P>
Signal Flow Platform for Mapping and Simulation of Vertebrate Retina for Sensor Systems
Cho, Kyoungrok,Baek, Seungbum,Cho, Sung-Wan,Kim, Jun-Ho,Goo, Yong Sook,Eshraghian, Jason K.,Iannella, Nicolangelo,Eshraghian, Kamran IEEE 2016 IEEE SENSORS JOURNAL Vol.16 No.15
<P>Our visual processing system is remarkably good; the retina is nothing like the CMOS image sensor, or for that matter, any of the vision processing architectures that have driven vision systems research for over three decades. Therefore, before embarking upon the complex task of architectural mapping of the retina into hardware, it is essential to gain a realistic insight into the theoretical functions of the retina. In addition, an understanding of the kinds of chemical/electrical interactions taking place must be ascertained in order to venture into the next insurmountable task - the simulation platform. This paper presents a generic signal flow architecture for the mapping of the vertebrate retina derived from ionic current movements and interactions. The approach pursued is focused on the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the architecture through transforming the system of nonlinear ordinary differential equations (ODEs) into an equivalent set of non-linear integral equations to cope with the singularity characteristic of retinal systems, providing an increase in the computational speed of similar to 36% when compared with the conventional ODE methods, thus enhancing the realization of a functional retina as part of future hardware-based sensor systems.</P>
Storage Logic Primitives Based on Stacked Memristor-CMOS Technology
Cho, Sung-Wan,Eshraghian, Jason,Eom, Ju-Song,Kim, Sungjin,Cho, Kyoungrok American Scientific Publishers 2016 Journal of Nanoscience and Nanotechnology Vol.16 No.12
<P>A newer and higher standard of circuits is emerging with the advent of memristive logic components. In the present paper memristor-CMOS (MCM)-based storage primitives are presented by exploiting the resistive switching property of the memristor. Practical implementation and fabrication of MCM-based logic circuits were verified by way of SPICE modeling, related simulations, and device characterization. The logic structure was designed by combining memristors with CMOS, and fabrication was performed by atomic layer deposition and an aluminum evaporation process in the form of a memristor on 350-nm CMOS technology. The proposed design method realized more efficient area utilization compared with current CMOS technology. As a result, the presented memristor-CMOS-based SR flip-flop and JK master slave flip-flop decreased the area by a factor of 31.2-52.2% with respect to the equivalent state memory CMOS circuits. The proposed memristor-CMOS technology allows for significant reduction of the silicon area, sustainability of Moore's law, and can be applied to increase the density of microchips.</P>
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture
Kyoungrok Cho,Sang-Jin Lee,Kavehei, Omid,Eshraghian, Kamran IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.7
<P>This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second.</P>
The fourth element: characteristics, modelling and electromagnetic theory of the memristor
Kavehei, O.,Iqbal, A.,Kim, Y. S.,Eshraghian, K.,Al-Sarawi, S. F.,Abbott, D. The Royal Society 2010 Proceedings, Mathematical, physical, and engineeri Vol.466 No.2120
<P> In 2008, researchers at the Hewlett-Packard (HP) laboratories published a paper in <I>Nature</I> reporting the development of a new basic circuit element that completes the missing link between charge and flux linkage, which was postulated by Chua in 1971 (Chua 1971 <I>IEEE Trans. Circuit Theory</I>18 , 507-519 ( doi:10.1109/TCT.1971.1083337 )). The HP memristor is based on a nanometre scale TiO 2 thin film, containing a- doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and non-volatile RAM, they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application-specific integrated circuits and field programmable gate arrays. A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for integrated circuits. This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell’s equations. We also review Chua’s arguments based on electromagnetic theory. </P>