Enhancement in Light Emission Efficiency of a Silicon Nanocrystal Light‐Emitting Diode by Multiple‐Luminescent Structures

Huh, Chul,Kim, Kyung&#x2010,Hyun,Kim, Bong Kyu,Kim, Wanjoong,Ko, Hyunsung,Choi, Chel‐,Jong,Sung, Gun Yong WILEY‐VCH Verlag 2010 Advanced Materials Vol.22 No.44

<P><B>The light output power and wall‐plug efficiency</B> of the Si nanocrystal (nc‐Si) light‐emitting diode (LED) were significantly enhanced by employing the multiple‐luminescent structures. This improvement was attributed to a strong confinement of carriers in the SiNx luminescent layers containing the nc‐Si due to the band offset between the luminescent layer and barrier layer. </P>

Microstructural and chemical properties of Cu‐In alloys formed using co‐electrodeposition

Moon, Kyung&#x2010,Won,Ashok Kumar, A.,Lee, Young&#x2010,Boo,Park, Yang&#x2010,Kyu,Choi, Chel‐,Jong John Wiley Sons, Ltd 2012 Surface and interface analysis Vol.44 No.11

<P>We investigated the microstructural and chemical properties of Cu‐In alloys formed on Au‐coated Si substrates using co‐electrodeposition. The co‐electrodeposition was performed using electrolytic solutions with various molar ratios of CuCl<SUB>2</SUB> and InCl<SUB>3</SUB> (1 mM/5 mM, 2 mM/4 mM, and 5 mM/5 mM) at room temperature. With increased electrodeposition current, the concentrations of Cu and In atoms in the Cu‐In alloys decreased and increased, respectively. Because of the preferential growth of Cu, a decrease in the molar ratio of CuCl<SUB>2</SUB> and InCl<SUB>3</SUB> led to a reduction in the minimum electrodeposition current that is required to obtain Cu‐In alloys with the same concentration of Cu and In atoms. The increases in electrodeposition current and the molar ratio of CuCl<SUB>2</SUB> and InCl<SUB>3</SUB> facilitated the formation of Cu‐In dendrites with long central trunks and secondary branches. The dendrites could be associated with autocatalytical alloy growth driven by a concentric diffusion field of metal ions on a thermodynamically unstable surface. During co‐electrodeposition using electrolytic solution (CuCl<SUB>2</SUB> = 1 mM and InCl<SUB>3</SUB> = 5 mM) under an electrodeposition current of 20 mA, the increase in the cathodic overpotential caused by surface irregularity led to the formation of Au‐In, which could be a main cause of the observed hillock formation. Copyright © 2012 John Wiley & Sons, Ltd.</P>

Effects of the flow rate of O₂ annealing ambient on structural and electrical properties of n+ emitter junctions formed using screen‐printed phosphorus diffusion process

Kim, Jin&#x2010,Sung,Yun, Hyung&#x2010,Joong,Seo, Min&#x2010,Woo,Janardhanam, V.,Ahn, Kwang&#x2010,Soon,Choi, Chel‐,Jong John Wiley Sons, Ltd 2012 Surface and interface analysis Vol.44 No.11

<P>We have investigated the effects of the flow rate of O<SUB>2</SUB> annealing ambient on the structural and electrical properties of the emitters with n+/p junctions formed using the screen printing of phosphorus (P) dopant paste, followed by O<SUB>2</SUB> annealing. The reaction between P‐paste and Si led to the formation of phosphorus silicate glass layer, of which P atoms were mostly segregated in surface and interface regions. The sheet resistance of the screen‐printed n+ emitters formed under O<SUB>2</SUB> flow rate of 5 l/min (LPM) was lower than that of 1 LPM. The recombination mechanism dominated the current transport in the forward bias regions of the screen‐printed n+ emitter, regardless of O<SUB>2</SUB> flow rate. The n+ emitter formed under O<SUB>2</SUB> flow rates of 5 LPM exhibited better rectification behavior with low reverse leakage, as compared with that of 1 LPM. The formation of thicker phosphorus silicate glass film caused by the increase in the O<SUB>2</SUB> flow rate resulted in the increase in the equilibrium concentration of Si interstitials in bulk Si and provided more P atoms being incorporated in n+/p emitter junction. The increases in maximum concentration of P atoms and junction depth caused by the increase in the O<SUB>2</SUB> flow rate could be responsible for superior junction quality of n+ emitter formed under O<SUB>2</SUB> flow rates of 5 LPM. Copyright © 2012 John Wiley & Sons, Ltd.</P>

Electrical and structural properties of Pd/V/<i>n</i>‐type InP (111) Schottky structure as a function of annealing temperature

Naik, S. Sankar,Rajagopal Reddy, V.,Choi, Chel‐,Jong,Bae, Jong&#x2010,Seong John Wiley Sons, Ltd. 2012 Surface and interface analysis Vol.44 No.1

<P><B>Abstract</B></P><P>Palladium/Vanadium (Pd/V) Schottky structures are fabricated on <I>n</I>‐type InP (100) and the electrical, structural and surface morphological characteristics have been studied at different annealing temperatures. The extracted barrier height of as‐deposited Pd/V/<I>n</I>‐InP Schottky diode is 0.59 eV (I–V) and 0.79 eV (C–V), respectively. However, the Schottky barrier height of the Pd/V Schottky contact slightly increases to 0.61 eV (I–V) and 0.84 eV (C–V) when the contact is annealed at 200 °C for 1 min. It is observed that the Schottky barrier height of the contact slightly decreases after annealing at 300, 400 and 500 °C for 1 min in N<SUB>2</SUB> atmosphere. From the above observations, it is clear that the electrical characteristics of Pd/V Schottky contacts improve after annealing at 200 °C. This indicates that the optimum annealing temperature for the Pd/V Schottky contact is 200 °C. Basing on the auger electron spectroscopy and X‐ray diffraction results, the formation of Pd‐In intermetallic compound at the interface may be the reason for the increase of barrier height upon annealing at 200 °C. The formation of phosphide phases at the Pd/V/<I>n</I>‐InP interface could be the reason for the degradation in the barrier heights after annealing at 300, 400 and 500 °C. From the AFM results, it is evident that the overall surface morphology of the Pd/V Schottky contacts is fairly smooth. Copyright © 2011 John Wiley & Sons, Ltd.</P>

Effects of post metallization annealing on modulation in effective work function of platinum gate electrode in germanium metal‐oxide‐semiconductor devices

Chandra, S. V. Jagadeesh,Hong, Woong&#x2010,Ki,Kim, Jin&#x2010,Sung,Hong, Hyobong,Choi, Chel‐,Jong Heyden & Son 2012 Surface and interface analysis Vol.44 No.11

<P>The inherent contributions of Fermi level pinning in Ge metal‐oxide‐semiconductor devices with Pt/HfO<SUB>2</SUB> gate stacks were investigated by examining the impact of thermal treatment in forming gas (FG) and oxygen environments on the effective metal work function (<I>Φ</I><SUB>m,eff</SUB>) of the Pt gate electrode. The <I>Φ</I><SUB>m,eff</SUB> of the Pt gate electrode for as‐deposited devices was extracted to be ~4.1 eV. However, the FG annealing process led to the increase in the <I>Φ</I><SUB>m,eff</SUB> of the Pt gate electrode up to ~4.5 eV, whereas no variation was noticed after oxygen annealing process. The interstitial hydrogen atoms with negative charge introduced by the FG annealing compensate positively charged dipoles associated with the Fermi level pinning of Ge. This could be responsible for the increased <I>Φ</I><SUB>m,eff</SUB> of the Pt gate electrode in FG‐annealed devices. Copyright © 2012 John Wiley & Sons, Ltd.</P>

Electrical, structural and morphological characteristics of rapidly annealed Ni/Pd Schottky rectifiers on <i>n</i>‐type GaN

Siva Pratap Reddy, M.,Rajagopal Reddy, V.,Jyothi, I.,Choi, Chel‐,Jong John Wiley Sons, Ltd. 2011 Surface and interface analysis Vol.43 No.9

<P><B>Abstract</B></P><P>Schottky rectifiers are fabricated on <I>n</I>‐type GaN using Ni/Pd metallization scheme and its characteristics have been investigated by current‐voltage (I‐V), Capacitance‐Voltage (C‐V), X‐Ray Diffraction (XRD) and SIMS measurements as a function of annealing temperature. The calculated Schottky barrier height of the as‐deposited contact was found to be 0.60 eV (I‐V), 0.71 eV (C‐V) with an ideality factor of 1.44. However, the barrier height slightly increases after annealing at 300, 400 and 500 °C. On the basis of the experimental results, a high‐quality Schottky contact with barrier height and ideality factor of 0.81 eV (I‐V), 0.88 eV (C‐V) and 1.13 respectively, can be obtained after annealing at 600 °C for 1 min in a nitrogen atmosphere. Further, after annealing at 700 °C, it is found that the barrier height slightly decreased to 0.74 eV (I‐V) and 0.85 eV (C‐V). From the above observations, one can note that Ni/Pd Schottky contact exhibits excellent electrical properties after a rapid thermal annealing at 600 °C. According to the SIMS and XRD analysis, the formation of gallide phases at the Ni/Pd/<I>n</I>‐GaN interface could be the reason of the barrier height increase at elevated annealing temperatures. The Atomic Force Microscopy (AFM) results show that the overall surface morphology of Ni/Pd Schottky contacts on <I>n</I>‐GaN is fairly smooth. The above observations reveal that Ni/Pd Schottky metallization scheme was a good choice for the fabrication of high‐temperature and high‐power device applications. Copyright © 2010 John Wiley & Sons, Ltd.</P>