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A 0.18-<tex> $\mu$</tex> m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver
Bongsub Song,Kyunghoon Kim,Junan Lee,Jinwook Burm IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.2
<P>A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10<SUP>-12</SUP> BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-μm standard CMOS technology with 0.3 × 0.8-mm<SUP>2</SUP> active area.</P>
An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory
Bongsub Song,Nayeon Cho,Byunghoon Kim,Jung-Han Choi,Young-Lok Kim,Jinwook Burm IEEE 2010 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.57 No.11
<P>An autofocus (AF) sensor with global shutters using offset-free frame memory is presented. A cross-shaped AF sensor array has left and right horizontal arrays and top and bottom vertical arrays. AF is achieved by calculating the phase difference from the digital code of the light illumination difference between the left and right (or top and bottom) arrays. The global shutter was implemented by using offset-free frame memories for accuracy enhancement. The proposed offset-free frame memories consist of flip-around sample-and-hold amplifiers with correlated double sampling. An active pixel sensor array, offset-free frame memories, a programmable gain amplifier, a 10-bit pipelined analog-to-digital converter, and digital control circuits are fully integrated on the chip fabricated on the 0.18-μm CMOS image sensor technology. It occupies 7 × 8 mm<SUP>2</SUP> with bonding pads. Each active pixel size is 15 × 100 μm<SUP>2</SUP>. The total power consumption of the AF sensor is 660 mW at 3.3-V supply voltage.</P>
SONG, Bongsub,KIM, Dohyung,KIM, Kwangsoo,BURM, Jinwook The Institute of Electronics, Information and Comm 2011 IEICE transactions on electronics Vol.94e.c No.5
<P>A sub-harmonic RF transmitter architecture with simultaneous power combination and carrier-leakage cancellation is proposed. It employs an 8-phase ring-type voltage controlled oscillator (VCO), sub-harmonic mixers, driver amplifiers, and a balun. A signal power is combined with its 180° phase-shifted signal through the balun. Simultaneously carrier-leakage generating in sub-harmonic mixers is canceled by its phase difference. The proposed transmitter achieved 1dBm 1-dB output compression point (<I>P</I><SUB>-1dB</SUB>) under 1.8V supply and -40dBm carrier-leakage in 5GHz band.</P>
A 0.18µm CMOS 12Gb/s 10-PAM Serial Link Transmitter
SONG, Bongsub,KIM, Kwangsoo,BURM, Jinwook The Institute of Electronics, Information and Comm 2011 IEICE transactions on electronics Vol.94e.c No.11
<P>A 12Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432mW such that the figure of merit of the transmitter is 36pJ/bit. The present work demonstrates the greater channel efficiency of 4bit/symbol than the currently reported multi-level PAM transmitters.</P>
Bongsub Song,Kyunghoon Kim,Junan Lee,Jinil Chung,Youngjung Choi,Jinwook Burm IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.61 No.9
<P>A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lower power dissipation than conventional 4-PAM drivers. As a result, the proposed 4-PAM transmitter implemented in a 0.13-μm CMOS process achieved 10-Gb/s data rate with only 13.5-mW power dissipation.</P>