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- 저자 : Aniruddh Bahadur Yadav (검색결과 1 건)
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Binay Binod Kumar,Shubham Kumar,Pramod Kumar Tiwari,Aniruddh Bahadur Yadav,Sarvesh Dubey,Kunal Singh 한국전기전자재료학회 2024 Transactions on Electrical and Electronic Material Vol.25 No.3
This paper explores possibility of device as well as circuit performance enhancement in the bottom gate ZnO based TFT via Mg and Cd material doping. DC, Analog & RF performance, Energy effi ciency and Noise analysis were erformed for both doped (i.e., MgyZn1−yO and CdxZn1−xO ) and undoped ZnO channel TFT structures. Further, successful ircuit implementation of these devices was done in resistive inverter and AMLCD pixel display circuits. Performance wise both MgyZn1−yO and CdxZn1−xO channel TFTs were found to be superior against its undoped variant. ~ 376%, ~ 105% nd ~ 162% are the percentage improvement in (ION∕IOFF) ratio, fi eld eff ect mobility (μFE) and eff ective mobility μeff) for CdxZn1−xO based TFT with respect to ZnO based TFT, same parameters show ~ 194%, ~ 103% and ~ 133% ercentage improvement for the case of MgyZn1−yO TFT. Also, ~ 23% is percentage decrease in subthreshold swing (SS) for CdxZn1−xO based TFT with respect to ZnO based, whereas ~ 11% is percentage decrement for MgyZn1−yO . Intrinsic gate delay, the percentage decrement is ~ 54.15 and ~ 59.95% for MgyZn1−yO and CdxZn1−xO respectively w.r.t ZnO. Both the CdxZn1−xO and MgyZn1−yO TFT shows unanimous decrease in delay for the resistive inverter as well as AMLCD pixel display circuits. The reported results shows that bottom gate CdxZn1−xO TFT has better performance for bove-mentioned performance parameters. The numerical simulations are performed on Silvaco ATLAS TCAD simulator.
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