http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
호정일,왕성근 대한생물치료정신의학회 2003 생물치료정신의학 Vol.9 No.1
Objectives : The purpose of this study was to evalute the effect of alcohol on sedation and some cognitive function(eg,daytime sleepiness, fatigue, and mood measured by multiple sleep latency test(MSLT) and visual analogue scale(VAS), vigilance, attention and short-term memory measured by Vienna Test System). Methods : 15 healthy, normal young college students participated in this study. Participating subjects were in good physical and psychological health and were asymptomatic as to sleep/wake complaints. Subjects visited our laboratory by 08 : 00 at the first day, and they had baseline MSLT and Test(at 9;00, 11;00, 14:00, and 16:00).Each time, the subjects completed VAS for sleepiness, fatigue and mood before they underwent an Vienna Test to evaluate their vigilance, attention and short-term memory. On the second day, subjects had 0.5g/kg of alcohol, the third day, subject had 1.0g/kg of alcohol, and repeated the same process as those of the first. Results : 0.5g/kg of alcohol reduced sleep latency after 1 hour, and 1.0g/kg of alcohol reduced sleep latency until 5 hours after administration significantly. 0.5g/kg of alcohol induced daytime sleepiness 1 hours after administration, and 1.0g/kg of alcohol induced daytime sleepiness and fatigue until 3 hours after administration, but there were no effects on mood. Vigilance was decreased significantly 1 hour after 0.5g/kg of alcohol administration, and attention and short-term memory were not changed significantly after alcohol administration. After alcohol adminstration(0.5-1.0g/kg), there were significant positive correlation between daytime sleepiness and fatigue, and fatigue and mood. Conclusion : It can be concluded that alcohol decreases sleep latency and induces daytime sleepiness and fatigue, and decreases vigilance in normal subjects.
저비용 FPGA를 이용한 AES 암호프로세서 설계 및 구현
호정일(Jung Il Ho),이강(Kang Yi),조윤석(Yun Seok Cho) 한국정보과학회 2004 한국정보과학회 학술발표논문집 Vol.31 No.1A
본 논문의 목적은 AES(Advanced Encryption Standard)로 선정된 Rijndael 암호 및 복호 알고리즘을 하드웨어로 설계하고 이를 저비용의 FPGA로 구현하는 것이다. 설계된 AES 암호프로세서는 20만 게이트 급 이하의 FPGA로 구현한다는 비용의 제약 조건 하에서 대용량의 데이터를 암호화, 복호화 하기에 적합한 성능을 가지도록 하였다. 또한 구현 단계에서는 설계한 AES 암호프로세서와 UART 모듈을 동일 FPGA 상에서 통합하여 실용성 및 면적 효율성을 보였다. 구현된 Rijndael 암호 프로세서는 20만 게이트를 갖는 Xilinx 사의 Spartan-II 계열의 XC2S200 칩 사용시 53%의 면적을 차지 하였고, Static Timing Analyzer로 분석한 결과 최대 29.3MHz 클럭에서 동작할 수 있고 337Mbps의 최대 성능을 가진다. 구현된 회로는 실제 FPGA를 이용하여 검증을 수행하였다.