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김남규(Nam-Kyu Kim),최성표(Sung-Phyo Choi),박현태(Hyun-Tae Park),엄지용(Ji-Yong Um) 대한전자공학회 2018 대한전자공학회 학술대회 Vol.2018 No.6
This brief presents a 10-bit 40-MS/s pipelined SAR ADC which employes a merged capacitor switching(MCS) scheme with top-plate sampling. A MCS scheme in the first MDAC of a pipelined SAR ADC, a reference-voltage reduction can occur which results in mismatch of reference voltage between adjacent stages. In order to compensate for the reference mismatch due to MCS scheme, a feedback capacitor of a residue amplifier is implemented as tunable. Also, this work proposes a modified class-AB telescopic op amp which facilitates power consumption reduction. A 10-bit 40-MS/s pipelined ADC is designed using a 0.18-μm CMOS process. In simulation, a step error between each segment in overall analog-to-digital transfer curve is corrected by controlling feedback capacitance, and the designed ADC dissipates a power consumption of 1.8 mW.