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차동 전하-전달 증폭기를 이용한 저전력 12 비트 확장계수 A/D 변환기 설계
송동규(Dongkyu Song),이상주(Sangjoo Lee),임신일(Shinil Lim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
This paper presents the design, analysis, and simulation results of a 12bit, 1.6KS/s extended counting A/D converter. At first, this converter operates as first-order ΣΔ modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. To reduce power consumption, the ADC uses the comparator which is composed of DCTA(differential charge transfer amplifier) and dynamic latch. With a 0.35㎛ CMOS technology, the simulation results show the SNR of 70㏈ and the power consumption of 200㎼ at a 3.3V supply voltage.
Rail-to-Rail의 입력 신호 범위를 가지는 12-bit 1MS/s 축차비교형 아날로그-디지털 변환기
김두연(DooYeoun Kim),정재진(JaeJin Jung),임신일(Shinil Lim),김석기(Suki Kim) 대한전기학회 2010 전기학회논문지 Vol.59 No.2
As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital(A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 ㏈ and Free-Dynamic-Range (SFDR) of 73 ㏈. The occupied active area is 0.6㎟