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A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator
이한열,정동길,황유정,이현배,장영찬 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6
A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and 620 × 340 μm2, respectively.
40MHz의 대역폭과 개선된 선형성을 가지는 Active-RC Channel Selection Filter
이한열,황유정,장영찬,Lee, Han-Yeol,Hwang, Yu-Jeong,Jang, Young-Chan 한국정보통신학회 2013 한국정보통신학회논문지 Vol.17 No.10
본 논문에서는 40MHz의 대역폭과 개선된 선형성을 가지는 active-RC channel selection filter (CSF)가 제안된다. 제안되는 CSF는 5차 butterworth 필터로써 한 단의 1차 low pass 필터와 두 단의 biquad 기반의 2차 low pass 필터, 그리고 DC offset 제거를 위한 DC 피드백 회로로 구성된다. CSF의 선형성을 개선하기 위해 스위치로 사용되는 MOSFET의 body를 source 노드로 연결한다. 설계된 CSF의 대역폭은 10MHz, 20MHz, 그리고 40MHz로 선택될 수 있으며, 전압 이득은 0dB에서 24dB까지 6dB의 단위로 조정된다. 제안된 CSF는 1.2V 40nm의 1-poly 8-metal CMOS 공정에서 설계된다. 설계된 CSF가 40MHz의 대역폭과 0dB의 gain을 가질 때, OIP3는 31.33dBm이고 in-band ripple은 1.046dB, IRN는 39.81nV/sqrt(Hz)로 시뮬레이션 검증되었다. CSF의 면적과 전력소모는 각각 $450{\times}210{\mu}m^2$와 6.71mW 이다. An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.
기하학적 불확실성 기반 영상 관성 항법의 원거리 특징점 감지
이한열(Han Yeol Lee),정재형(Jae Hyung Jung),박찬국(Chan Gook Park) 제어로봇시스템학회 2021 제어·로봇·시스템학회 논문지 Vol.27 No.11
In this paper, we propose a new method that classifies the features in a visual-inertial navigation system. The far features provide inaccurate information on the position and velocity of a moving vehicle, and thus, the information provided by the far features should be used for attitude estimation without recovering the feature depths. In contrast, the information obtained from the near features can be used to obtain a reliable depth estimate because of the large parallax in the image plane. However, the criterion for labeling the features as near or far features is ambiguous. Previously, various geometric classification methods based on a stereo camera and measurement uncertainties have been reported. Herein, we present a criterion based on the geometric method using the MSCKF (Multi-State Constraint Kalman filter ). Additionally, we define a new concept — depth uncertainty — as the criterion of feature classification in the MSCKF. Using this criterion, we can draw a limited range defined as the observable region. Implementation of this method can decrease the error caused by the low parallax of the feature. The proposed method is validated through simulations and experiments, showing a 12.7 % and 21.2 % decrease in the mean position error, respectively, using the far features classification.