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고온 열처리 공정이 탄화규소 쇼트키 다이오드 특성에 미치는 영향
정희종,방욱,강인호,김상철,한현숙,김형우,김남균,이용재,Cheong, Hui-Jong,Bahng, Wook,Kang, In-Ho,Kim, Sang-Cheol,Han, Hyun-Sook,Kim, Hyeong-Woo,Kim, Nam-Kyun,Lee, Yong-Jae 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.9
The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.
P형 우물 영역의 도핑 농도와 면적에 따른 4H-SiC 기반 DMOSFET 소자 구조의 최적화
안정준,방욱,김상철,김남균,정홍배,구상모,Ahn, Jung-Joon,Bahng, Wook,Kim, Sang-Chul,Kim, Nam-Kyun,Jung, Hong-Bae,Koo, Sang-Mo 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.7
In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from $1\;{\times}\;10^{17}\;cm^{-3}$ to $5\;{\times}\;10^{17}\;cm^{-3}$ and doping depth from $0.5\;{\mu}m$ to $1.0\;{\mu}m$. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.
이온주입 공정을 이용한 4H-SiC p-n Diode에 관한 시뮬레이션 연구
이재상,방욱,김상철,김남균,구상모,Lee, Jae-Sang,Bahng, Wook,Kim, Sang-Cheol,Kim, Nam-Kyun,Koo, Sang-Mo 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.2
Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used Monte-Carlo method. We simulated the effect of channeling by Al implantation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the effect of varying the implantation energies and the corresponding doses on the distribution of Al in 4H-SiC. The controlled implantation energies were 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2{\times}10^{14}$ to $1{\times}10^{15}\;cm^{-2}$. The Al ion distribution was deeper with increasing implantation energy, whereas the doping level increased with increasing dose. The effect of post-implantation annealing on the electrical properties of Al-implanted p-n junction diode were also investigated.
조영득,방욱,김상철,김남균,구상모,Jo, Yeong-Deuk,Bahng, Wook,Kim, Sang-Cheol,Kim, Nam-Kyun,Koo, Sang-Mo 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.8
The local oxidation using an atomic force microscopy (AFM) is useful for Si-based fabrication of nanoscale structures and devices. SiC is a wide band-gap material that has advantages such as high-power, high-temperature and high-frequency in applications, and among several SiC polytypes, 4H-SiC is the most attractive polytype due to the high electron mobility. However, the AFM local oxidation of 4H-SiC for fabrication is still difficult, mainly due to the physical hardness and chemical inactivity of SiC. In this paper, we investigated the local oxidation of 4H-SiC surface using an AFM. We fabricated oxide patterns using a contact mode AFM with a Pt/Ir-coated Si tip (N-type, 0.01-0.025 ${\Omega}cm$) at room temperature, and the relative humidity ranged from 40 to 50 %. The height of the fabricated oxide pattern (1-3 nm) on SiC is similar to that of typically obtained on Si ($10^{15}^{\sim}10^{17}$ $cm^{-3}$). We perform the 2-D simulation to further analyze the electric field between the tip and the surface. We demonstrated that a specific electric field (4 ${\times}$ $10^7\;V/m$) and a doping concentration ($^{\sim}10^{17}$ $cm^{-3}$) is sufficient to switch on/off the growth of the local oxide on SiC.
에피층 농도 변화에 따른 Multi-RESURF SOI LDMOSFET의 전기적 특성 분석
김형우,서길수,방욱,김기현,김남균,Kim, Hyoung-Woo,Seo, Kil-Soo,Bahng, Wook,Kim, Ki-Hyun,Kim, Nam-Kyun 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.9
In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from $2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$ to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is $224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.
800 V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션
최창용,강민석,방욱,김상철,김남균,구상모,Choi, Chang-Yong,Kang, Min-Seok,Bahng, Wook,Kim, Sang-Cheol,Kim, Nam-Kyun,Koo, Sang-Mo 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.8
In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.
표면 도핑 기법을 사용한 SOI RESURF LDMOSFET의 항복전압 및 온-저항 특성 분석
김형우,김상철,방욱,강인호,김기현,김남균,Kim Hyoung-Woo,Kim Sang-Cheol,Bahng Wook,Kang In-Ho,Kim Kl-Hyun,Kim Nam-Kyun 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.1
In this paper, breakdown voltage and on-resistance characteristics of the surface doped SOI RESURF LDMOSFET were investigated as a function of surface doping depth. In order to verify the variation of characteristics, two-dimensional device simulation was carried out. Breakdown voltage of the proposed structure is varied from $73 {\~}138V$ while surface doping depth varied from $0.5{\~}2.0{\mu}m$. And on-resistance is decreased from $0.18{\~}0.143{\Omega}/cm^2$ while surface doping depth increased from $0.5 {\~}2.0{\mu}m$. Maximum breakdown voltage of the proposed structure is 138 V at $1.5{\mu}m$ depth of surface doping, yielding $22.1\%$ of improvement of breakdown voltage in comparison with that of the conventional SOI RESURF LDMOSFET with same epi-layer concentration. On-resistance characteristic is also improved about $21.7\%$.
벗김강도 측정법에 의한 파워 모듈의 솔더접합 특성 평가
김남균,이희흥,방욱,서길수,김은동,Kim, Nam-Kyun,Lee, Hee-Heung,Bahng, Wook,Seo, Kil-Soo,Kim, Eun-Dong 한국전기전자재료학회 2003 전기전자재료학회논문지 Vol.16 No.12
The strength and characteristics of the soldering interface of the power semiconductor chip in a power module has been firstly surveyed by the peel strength measurement method. A power module is combined with several power chips which generally has 30∼400$\textrm{mm}^2$ chip area to allow several tens or bigger amps in current rating, so that the traditional methods for interface characterization like shear test could not be applied to high power module. In this study power diode modules were fabricated by using lead-tin solder with 10${\times}$10$\textrm{mm}^2$ or 7${\times}$7$\textrm{mm}^2$ soldering interface. The peel strengths of soldered interfaces were measured and then the microscopic investigation on the fractured surfaces were followed. The peel test indicated that the crack propagated either through the bulk of the soft lead-tin solder which has 55-60 kgf/cm peel strength or along the interface between the solder and the plated nickel layer which has much lower 22 kgf/cm strength. This study showed that the peel test would be a useful method to quantify the solderability as well as to recognize which is the worst interface or the softest material in a power module with a large soldering area.
KOH Etching을 통한 4H-SiC Epitaxy 박막에서의 전위결함 거동
신윤지,김원정,문정현,방욱,Shin, Yun-Ji,Kim, Won-Jeong,Moon, Jeong-Hyun,Bahng, Wook 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.10
The morphology of etch pits in commercial 4H-SiC epi-wafer were investigated by molten-KOH etching. The etching process was optimized in $525{\sim}570^{\circ}C$ at 2~10 min and the novel type of etch pits was revealed. This type of etch pits have been considered as TED (threading edge dislocation) II, its origin and nature, however, are not reported yet. In this work, the morphology and evolution of etch pits during epitaxial growth were analyzed and the different behavior between TED and TEDII was discussed.
AI 이온 주입된 p-type 4H-SiC에 형성된 Ni/AI 오믹접촉의 전기 전도 특성
주성재,송재열,강인호,방욱,김상철,김남균,이용재,Joo, Seong-Jae,Song, Jae-Yeol,Kang, In-Ho,Bahng, Wook,Kim, Sang-Cheol,Kim, Nam-Kyun,Lee, Yong-Jae 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.9
Ni/Al ('/' denotes deposition sequence) contacts were deposited on Al-implanted 4H-SiC for ohmic contact formation, and the conduction properties were characterized and compared with those of Ni-only contacts. The thicknesses of the Ni and Al thin film were 30 nm and 300 nm, respectively, and the films were sequentially deposited bye-beam evaporation without vacuum breaking. Rapid thermal anneal (RTA) temperature was varied as follows : $840^{\circ}C$, $890^{\circ}C$, and $940^{\circ}C$. The specific contact resistivity of the Ni contact was about $^{\sim}2\;{\pm}\;10^{-2}\;{\Omega}{\cdot}cm^2$, However, with the addition of Al overlayer, the specific contact resistivity decreased to about $^{\sim}2\;{\pm}\;10^{-4}\;{\Omega}{\cdot}cm^2$, almost irrespective of RTA temperature. X-ray diffraction (XRD) analysis of the Ni contact confirmed the existence of various Ni silicide phases, while the results of Ni/Al contact samples revealed that Al-contaning phases such as $Al_3Ni$, $Al_3Ni_2$, $Al_4Ni_3$, and $Ab_{3.21}Si_{0.47}$ were additionally formed as well as the Ni silicide phases. Energy dispersive spectroscopy (EDS) spectrum showed interfacial reaction zone mainly consisting of Al and Si at the contact interface, and it was also shown that considerable amounts of Si and C have diffused toward the surface. This indicates that contact resistance lowering of the Ni/Al contacts is related with the formation of the formation of interfacial reaction zone containing Al and Si. From these results, possible mechanisms of contact resistance lowering by the addition of Al were discussed.