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이중 일함수 게이트 구조를 갖는 CMOS 소자의 전기적 특성
나기열(Kee-Yeol Na),신윤수(Yoon-Soo Shin),김영식(Young-Sik Kim),이광규(Kwang-Kyu Lee),최홍규(Hong-Kyu Choi),김성준(Sungjoon Kim),김영석(Yeong-Seuk Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metal-oxide-semiconductor field effect transistor (MOSFET) device, the poly-silicon gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-silicon gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices.
MEMS 공정을 이용한 32x32 실리콘 캔틸레버 어레이 제작 및 특성 평가
김영식,나기열,신윤수,박근형,김영석,Kim Young-Sik,Na Kee-Yeol,Shin Yoon-Soo,Park Keun-Hyung,Kim Yeong-Seuk 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.10
This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.
SOI 기판을 이용한 Thermal Probe 어레이 제작 및 특성 평가
조주현,나기열,박근형,이재봉,김영석,Cho, Ju-Hyun,Na, Kee-Yeol,Park, Keun-Hyung,Lee, Jae-Bong,Kim, Yeong-Seuk 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.11
This paper reports the fabrication and characterization of $5\;\times\;5$ thermal cantilever array for nano-scaled memory device application. The $5\;\times\;5$ thermal cantilever array with integrated tip heater has been fabricated with MEMS technology on SOI wafer using 7 photo masking steps. All single-level cantilevers have a diode in order to eliminate any electrical cross-talk between adjacent tips. Electrical measurements of fabricated thermal cantilever away show its own thermal heating mechanism. Thermal heating is demonstrated by the reflow of coated photoresist on the cantilever array surface.
게이트와 드리프트 영역 오버랩 길이에 따른 LDMOST 전력 소자의 전기적 특성
하종봉,나기열,조경록,김영석,Ha, Jong-Bong,Na, Kee-Yeol,Cho, Kyoung-Rok,Kim, Yeong-Seuk 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.7
In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.
0.25 μm 표준 CMOS 로직 공정을 이용한 Single Polysilicon EEPROM 셀 및 고전압소자
신윤수,나기열,김영식,김영석,Shin, Yoon-Soo,Na, Kee-Yeol,Kim, Young-Sik,Kim, Yeong-Seuk 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.11
For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.
이중 일함수 구조를 적용한 N-채널 EDMOS 소자의 항복전압 및 온-저항 특성
김민선,백기주,김영석,나기열,Kim, Min-Sun,Baek, Ki-Ju,Kim, Yeong-Seuk,Na, Kee-Yeol 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.9
In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).
신윤수(Yoon-Soo Shin),나기열(Kee-Yeol Na),최홍규(Hong-Kyu Choi),이광규(Kwang-Kyu Lee),김성준(Sung-Joon Kim),김영식(Young-Sik Kim),김영석(Yeong-Seuk Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, in order to supply program and erase voltages for embedded EEPROM, charge-pump circuit with output voltage of the maximum 10 V is proposed based on a 0.25 ㎛ standard CMOS logic process. To gain reliability for generated high voltage when charge-pump operates, high-voltage n-channel LDMOST device is developed and applied to charge-pump circuit. As a result of measurements, the fabricated high-voltage n-channel LDMOST device operation voltage is over 10 V and charge-pump exhibits output voltage range from 6.8 to 10 V for control voltage (Vctrl) sweeps from 0 to 1.5 V.
아날로그 응용을 위한 DWFG MOSFET의 매크로 모델 및 연산증폭기 설계
하지훈,백기주,이대환,나기열,김영석,Ha, Ji-Hoon,Baek, Ki-Ju,Lee, Dae-Hwan,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.8
In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.
바디 구동 차동 입력단과 Self-cascode 구조를 이용한 0.5 V 2단 연산증폭기 설계 및 제작
김정민,이대환,백기주,나기열,김영석,Gim, Jeong-Min,Lee, Dae-Hwan,Baek, Ki-Ju,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.4
This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.
Native-V<sub>th</sub> MOSFET을 이용한 셀프-캐스코드 구조의 아날로그 성능 분석
이대환,백기주,하지훈,나기열,김영석,Lee, Dae-Hwan,Baek, Ki-Ju,Ha, Ji-Hoon,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.8
The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.