http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
인간 면역겹핍 바이러스 음성인 환자에서 구인두 및 하인두에 걸쳐 발생한 카포시 육종 1예
나경진,안동빈,석준호,박준식 대한이비인후과학회 2012 대한이비인후과학회지 두경부외과학 Vol.55 No.1
The number of patients diagnosed with Kaposi’s sarcoma has grown steadily since it was first discovered in 1972 by Moric Kaposi, a Hungarian dermatologist. Kaposi’s sarcoma can be classified into four subtypes according to clinical form, epidemiology, and prognosis: idiopathic, endemic or African, immunosuppresion related, and acquired immunodeficiency syndrome related or epidemic Kaposi’s sarcoma. A single idiopathic Kaposi’s sarcoma in the head and neck area is very rarely found in an immunocompetent person. We experienced a case of Kaposi’s sarcoma of the oropharynx and hypopharynx. The patient was healthy 70-year-old man and had no signs of being human immunodeficiency virus positive or immunocompromised. The patient was treated with inductive chemotherapy using capecitabine (Xeloda®)/cisplatin followed by radiotherapy to a total 54 Gy.
1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS 전류모드 아날로그-디지털 변환기
최경진,이해길,나유찬,신홍규 한국음향학회 1999 韓國音響學會誌 Vol.18 No.2
본 논문에서는 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS IADC(Current-mode Analog-to-Digital Convener)를 제안한다. 전체적인 IADC의 선형성 향상을 위하여 CFT(Clock Feedthrough)가 제거된 9-비트 해상도 CSH를 설계하여 각 비트 셀 전단에 배치하였다. 제안한 IADC를 구성하는 비트 셀은 2개의 래치 CCMP를 사용하기 때문에 디지털 교정 로직이 간소화되고 소비전력이 감소된다. 또한 IADC를 구성하는 모든 블록들의 회로는 MOS 트랜지스터로만 설계되었기 때문에 혼성모드 집적화에 유리하다. 제안한 IADC를 현대 0.8 ㎛ CMOS 파라미터로 HSPICE 시뮬레이션 결과, 20Ms/s에서 100 ㎑의 입력 신호에 대한 SNR은 43 dB로 7-비트의 해상도를 만족하였고 27 ㎽의 소비전력 특성을 나타냈다. In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.