무선 센서 네트워크에서의 구조물 모니터링을 위한 효율적인 배터리 소모 기법

김선환(Seon-Hwan Kim),박창현(Chang-Hyeon Park) 한국통신학회 2008 한국통신학회 학술대회논문집 Vol.2008 No.7

플래시 메모리 기반 인덱스 구조에서 대리블록 이용한 가비지 컬렉션 기법

김선환(Seon Hwan Kim),곽종욱(Jong Wook Kwak) 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.6

낸드 플래시 메모리는 빠른 접근 시간과 저전력의 특성을 가지고 있어 저장장치로 많이 사용되고 있는 추세이다. 하지만 저사양의 임베디드 장치에서는 메모리 요구사항과 구현상의 복잡성으로 FTL을 적용하기에는 비용이 많이든다. 이러한 이유로 FTL을 구현하기 힘든 임베디드 장치에 적용할 수 있는 B+ 트리 연구들이 다수 제안되었다. 이런 연구들은 낸드 플래시 메모리에서 제자리 업데이트가 불가하다는 단점을 고려하여 삽입과 갱신의 성능을 최적화 하였다. 하지만 B+ 트리에 기존의 가비지 컬렉션 기법들을 적용하면 낸드 플래시 메모리의 페이지 위치를 변경하게 되고 B+ 트리의 재구성을 발생시켜 전체적인 성능을 저하시킨다. 이러한 문제를 해결하고자 본 논문에서는 낸드 플래시 메모리를 기반으로 하는 B+ 트리와 이와 유사한 인덱스 트리 구조에 적용할 수 있는 가비지 컬렉션 기법을 제안한다. 제안하는 가비지 컬렉션 기법은 블록 정보 테이블과 대리 블록을 이용하여 B+ 트리의 재구성을 발생시키지 않는다. 제안된 기법의 성능평가를 위해, 낸드 플래시 메모리가 장착된 실험 장치에 B+ 트리와 μ-Tree를 구현하고 제안된 기법을 적용하였다. 구현 결과 B+ 트리에서 제안된 기법이 GAGC(Greedy Algorithm Garbage Collection)보다 삽입된 키의 개수가 약 73% 많았으며, μ-Tree에서 제안된 기법이 GAGC보다 시간 오버헤드가 약 39% 적었다. Recently, NAND flash memories are used for storage devices because of fast access speed and low-power. However, applications of FTL on low power computing devices lead to heavy workloads which result in a memory requirement and an implementation overhead. Consequently, studies of B+-Tree on embedded devices without the FTL have been proposed. The studies of B+-Tree are optimized for performance of inserting and updating records, considering to disadvantages of the NAND flash memory that it can not support in-place update. However, if a general garbage collection method is applied to the previous studies of B+-Tree, a performance of the B+-Tree is reduced, because it generates a rearrangement of the B+-Tree by changing of page positions on the NAND flash memory. Therefor, we propose a novel garbage collection method which can apply to the B+-Tree based on the NAND flash memory without the FTL. The proposed garbage collection method does not generate a rearrangement of the B+-Tree by using a block information table and a proxy block. We implemented the B+-Tree and μ-Tree with the proposed garbage collection on physical devices with the NAND flash memory. In experiment results, the proposed garbage collection scheme compared to greedy algorithm garbage collection scheme increased the number of inserted keys by up to about 73% on B+-Tree and decreased elapsed time of garbage collection by up to about 39% on μ-Tree.

NAND 플래시 메모리 기반 B+ 트리에서 페이지 매핑 로그를 이용한 색인 관리 기법

김선환(Seon Hwan Kim),곽종욱(Jong Wook Kwak) 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.5

낸드 플래시 메모리는 저전력, 빠른 접근 속도, 저렴한 가격 등의 특징을 가지고 있어 저장장치로 널리 사용되고 있다. 하지만 낸드 플래시 메모리는 제자리 덮어쓰기가 지원되지 않아 기존의 하드 디스크 기반 응용 프로그램을 구동하기 위해서는 FTL(Flash Translation Layer)이 필요하다. FTL은 주소 매핑, 가비지 컬렉션, 마모도 균등화 작업 등을 포함하고 있어 저사양 임베디드 장치에 구현하기에는 메모리와 연산에 대한 비용이 많이 든다. 그래서 이런 장치들을 위해 낸드 플래시 메모리에 최적화된 색인 자료구조들이 연구되고 있다. 연구된 방법들은 쓰기에 소요되는 시간을 줄여 성능을 향상시켰지만 레코드 탐색에 소요되는 시간이 증가된다는 단점을 가지고 있다. 레코드 탐색시간을 증가시키지 않고 쓰기 횟수를 줄이기 위해 본 논문에서는 페이지 매핑 로그 테이블을 이용한 색인 관리 기법을 제안한다. 낸드 플래시 메모리의 단점인 제자리 덮어쓰기 불가로 인해 발생하는 페이지 쓰기 횟수를 줄이기 위해 매핑 로그 테이블은 B+ 트리에서 변경된 노드 페이지 주소를 저장하고 레코드 검색 시 이를 이용한다. 실험 평가를 통해 제안된 기법은 다른 기법들과 비교 시 레코드 탐색에서 발생하는 페이지 읽기 횟수를 최대 약 61% 줄였으며, 레코드 삽입에서 페이지 쓰기 횟수를 최대 약 31% 줄일 수 있었다. NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in B?-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

Sampling-based Block Erase Table in Wear Leveling Technique for Flash Memory

Seon Hwan Kim(김선환),Jong Wook Kwak(곽종욱) 한국컴퓨터정보학회 2017 韓國컴퓨터情報學會論文誌 Vol.22 No.5

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.

무선 센서네트워크에서 최단경로를 고려한 송신전력제어기법

김선환(Seon-Hwan Kim),박창현(Chang-Hyeon Park),이명섭(Myung-Sup Lee) 한국통신학회 2009 韓國通信學會論文誌 Vol.34 No.4

무선 센서네트워크에서 에너지 절약을 위해 필요한 송신전력을 제어하는 기법들이 많이 연구 되었다. 그러나 기존 연구들은 송신전력제어 과정에서 최적화된 송신전력 단계를 계산하기 위해 많은 패킷이 필요하다. 본 논문에서는 추가적인 제어 패킷을 발생시키지 않고 최단경로를 고려하는 송신전력제어기법을 제안한다. 그 기법은 네트워크 구성에 필요한 광고 메시지를 최대한 활용하여 제어 패킷을 사용하지 않으며 네트워크 구성 초기에 최대 송신전력 단계로 광고 메시지를 전달하여 구성된 최단경로를 기준으로 한다. 제안한 기법의 평가를 위해 TinyOS에서 제안한 기법을 적용하였다. 그리고 21개의 노드를 이용하여 네트워크를 구성하고 평균 전류 소모량, 평균 네트워크 깊이 등을 측정하였다. 측정한 결과 제안한 기법을 적용한 네트워크가 이전보다 송신 시 평균 전류량이 약 24.7%만큼 적으며 네트워크의 홉 수가 일반 네트워크 홉 수보다 약 41% 적었다. There are a number of studies that propose transmission power control algorithms in wireless sensor networks. However, these algorithms have a lot of overhead in the initialization phase since a number of packets have to be transmitted to determine the optimal transmission power level. This paper proposes the transmission power control technique considering the shortest-path to minimize the hop-count without the occurrence of any power control messages. We applied the proposed technique on tree-based network component implemented on TinyOS. And we evaluated the performance including transmission energy and average network depth with 21 motes. Compared to before, the proposed technique reduces about 24.7% of the average electric current on transmitting. As a result of considering the shortest-path, the hop-count considering the shortest-path was about 41% less than a normal network.

CoCl₂ 처리로 유도된 hypoxia상태에서 세포자살과 ER stress에 관련된 인자의 발현

Seon-Hwan Kim(김선환),Hyon-Jo Kwon(권현조),Hyeon Song Koh(고현송),Shi-Hun Song(송시헌),Kisang Kwon(권기상),O-Yu Kwon(권오유),Seung Won Choi(최승원) 한국생명과학회 2010 생명과학회지 Vol.20 No.12

PC12 세포에서 CoCl₂에 의한 hypoxia 유도는 HIF1 alpha의 상승 발현으로 확인하였다. 이때 apoptosis의 유도는 genomic DNA의 fragmentation과 apoptotic body는 Hoechst 염색으로 확인되었고, ER luminal chaperone의 발현 및 ER stress signal에 관여하는 ER membrane kinase인 IRE1, PERK, ATF6의 발현도 확인되었다. 이들이 apoptosis로 연결되는 고리 역할을 하는 IRE1-XBP1 mRNA splicing, PERK-eIF2 alpha, ATF6 protein cleavage도 반응하는 것으로 확인되었다. 위의 결과는 신경세포의 hypoxia상태는 ER stress signal pathway를 거쳐서 apoptosis가 된다는 것을 증명한 것으로 신경세포의 hypoxia치료를 위한 기초 자료가 될 것으로 생각한다. Cobalt(Ⅱ) chloride, a chemical compound with the formula CoCl₂, has been widely used in the treatment of anemia, as a chemical agent for the induction of hypoxia in cell cultures, and is known to activate hypoxic signaling. However, excessive exposure to cobalt is associated with several clinical conditions, including asthma, pneumonia, and hematological abnormalities, and can lead to tissue and cellular toxicity. It is also known to induce apoptosis. One of the questions was that of whether CoCl₂ might induce apoptosis via endoplasmic reticulum (ER) stress in neurons. To address this question, first, the level of DNA fragmentation was measured for assay of apoptotic rates using CoCl₂ with neuron PC12 cells. After confirmation of apoptosis inductions, under the same conditions, the expression levels of ER stress associated factors [ER chaperones Bip, calnexin, ERp72, ERp29, PDI, and ER membrane kinases (IRE1, ATF6, PERK)] were examined by RT-PCR and Western blotting. These results indicated that apoptosis is induced through activation of ER membrane kinases via ER stress. In conclusion, during induction of apoptosis through CoCl₂-induced hypoxia in neuron PC12 cells, ER membrane kinase of IRE1 was dominantly up-expressed, and, consecutively, TRAF2, which has been suggested to be one of the links connecting apoptosis and ER stress, was strongly up-expressed.

플래시 메모리에서 비트 배열과 비트 설정 임계값을 이용한 마모도 평준화 기법

김선환(Seon Hwan Kim),곽종욱(Jong Wook Kwak),박창현(Chang-Hyeon Park) 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.11

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

연수의 낭종성 혈관아세포종 1예 -증례보고-

김선환 ( Seon Hwan Kim ),송시헌 ( Shi Hun Song ),고현송 ( Hyeon Song Koh ),염진영 ( Jin Young Youm ),김윤 ( Youn Kim ) 대한뇌종양학회 2002 대한뇌종양학회지 Vol.1 No.1

Hemangioblastomas of the medulla oblongata are benign vascular neoplasms that malignantly locate. Most of tumors are solid and cystic natures are extremely rare in medulla oblongata. We experienced a cystic hemangioblastoma located in medulla oblongata and successful treated by surgical excision. A 47-year-old man with a 3-months history of paresthesia on left upper extremity and trunk. MRI revealed a cystic mass with enhancing small nodule on dorsal portion of medulla oblongata. Using a suboccipital craniectomy the tumor was totally removed. The authors report a rare case of cystic hemangioblastoma in medulla oblongata and review the literatures.

리듬청각자극을 동반한 기능적 전기자극 보행훈련이 뇌졸중 환자의 균형과 보행능력에 미치는 영향

김선환 ( Seon-hwan Kim ),김영민 ( Young-min Kim ) 대한물리의학회 2018 대한물리의학회지 Vol.13 No.4

PURPOSE: The present study was conducted to investigate the effects of functional electrical stimulation gait training with rhythmic auditory stimulation on balance and gait ability in stroke patients. METHODS: In this blinded randomized controlled study, 26 stroke patients were assigned to either experimental group (n=13) consisting of 30 min of gait training 5 days per week for 4 weeks while performing functional electrical stimulation gait training with rhythmic auditory simulation, or a control group (n=13) performing the same gait training program, also consisting of 30 minutes 5 days a week and lasting for 4 weeks, but without functional electrical stimulation and rhythmic auditory stimulation. At baseline and after the 4 week intervention, balance was measured using the timed up and go test (TUG). Gait velocity was measured using the 10-meter walk test (10 MWT) and gait ability was assessed using the functional gait assessment (FGA). RESULTS: After the intervention, the experimental group showed statistically significant differences in gait velocity and ability (10 MWT, FGA) (p<.05). Between-group differences were statistically significant in gait velocity and ability (10 MWT, FGA) (p<.05). CONCLUSION: The findings suggest that functional electrical stimulation gait training with a rhythmic auditory stimulation gait training program may help improve gait ability in stroke patients.

저등급 자궁내막 간질성 육종 3예

고선환 ( Go Seon Hwan ),송은섭 ( Song Eun Seob ),김세련 ( Kim Se Lyeon ),이문희 ( Lee Mun Hui ),김우철 ( Kim U Cheol ),송윤섭 ( Song Yun Seob ),박지현 ( Park Ji Hyeon ),임문환 ( Im Mun Hwan ),이병익 ( Lee Byeong Ig ),이우영 ( Lee 대한산부인과학회 2004 Obstetrics & Gynecology Science Vol.47 No.4

Endometrial stromal sarcomas (ESS) of the myometrium compose just 0.2% of uterine malignant tumors. In terms of their cellular mitotic activities, they are named as low grade or high grade ESS. As low grade ESS are very rare, we would like to report our 3