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2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계
정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),고귀한(Gui-han Ko),조성익(Seong-Ik Cho) 대한전기학회 2012 전기학회논문지 Vol.61 No.2
A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.