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RISS 인기검색어
- 검색키워드
- 주제어 : Berlekamp-Massey algorithm (검색결과 3 건)
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알고리즘별 On-die ECC 부·복호화기 설계 및 결과 분석
Demand for high-speed and high-capacity DRAM is increasing, DRAM has been highly integrated accordingly. This high integration has caused the bit error rate(BER) of the DRAM, in order to solve this problem, On-die ECC which applied ECC on DRAM has been proposed. This thesis identifies the BCH code based algorithm that is easy to correct multiple errors according to the increasing BER, and compare the performance in the hardware environment. In this paper, introduce various algorithm used in the encoding-decoding process based on BCH code that are easy to correct multiple errors, and present hardware structures of various algorithms. The proposed structure is designed with Verilog HDL and the performance is measured after synthesis using Design Compiler. Based on the results of the performance, compare and analyze the results for selecting the appropriate algorithm and structure as On-die ECC structure.
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On the merit factor and linear complexity of polyphase sequences
문경하 Graduate School, Yonsei University 2004 국내석사
Merit factor는 다상 부호열의 비주기 자기상관 특서에 대한 중요한 기준이 된다. 본 논문에서는 이러한 merit factor의 관점에서 가장 우수한 비주기 자기상관특성을 갖는 새로운 다상 부호열을 제안하며, 제안된 부호열을 기존의 잘 알려진 다상 부허열과 함께 생성방법에 따라 분류한다. 다음으로, 선형 궤한 시프트 레지스터와 선형복잡도의 기본적인 관계와 실제 응용에서 다상 부호열을 발생시키기 위한 Berlekamp-Massey알고리름과 Reeds-Sloane알고리즘에 대해 논의한다. 그리고, 각각의 다상 부호열에 대한 merit factor를 실험적으로 비교 분석하며, 일반적인 구현의 관점에서 선형 궤한 쉬프트 레지스터를 이용해 field에서 다상 부호열을 생성할 수 없는 이유에 대하여 알아본 후, interger redidue ring에서 다상 부호열 생성기의 구현방법을 제안한다. 또한, 제안된 구현방법에 의해 다상 부호열들의 선형복잡도를 분석한다. In this paper, we propose the new polyphase sequence with the best nonperiodic autocorrelation property in the viewpoint of the merit factors, which are important criteria for a nonperiodic autocorrelation property. Also, we classify well-known polyphase sequences and the proposed sequence according to construction methods. Next, we study the basic relation between the linear feedback shift register (LFSR) and the linear complexity (LC), and mention Berlekamp-Massey algorithm and Reeds-Sloane algorithm to concentrate our attention on the problem which is to generate polyphase sequences in applications. And we compare the merit factors for every polyphase sequence. And, in the view of the general implementation, we discuss the reason why we can't generate a polyphase sequence over a field, and propose the implementation method of a polyphase sequence generator over an integer residue ring. Also, we analyze the LC of polyphase sequences by the proposed implementation method.
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In communication and memory systems, ECC based on BCH code is being used and studied to improve data reliability, security, and memory productivity. The addition of ECC operations during data processing leads to an increase in latency. In the future, communication and memory systems that will become faster as technology advances will require shorter latency for ECC. However, the Berlekamp-Massey Algorithm (BMA) that generates the error locator polynomial of the BCH code requires repetitive computation as much as the error correction capability. So, it has the most complex and long latency among BCH code operations. This paper presents a method of reducing the latency of BCH-based BMA and iBMA (inversionless BMA) pipelined circuits. The initial stage of BMA and iBMA can be calculated as a combination of the input syndrome. In this way, this paper proposes a method to reduce latency by omitting the first stage of BMA and iBMA. The proposed method can reduce latency as much as the time required for one stage of BMA and iBMA. In addition, double error correction has a shorter latency than systolic iBMA, which is known to be the fastest. Through this study, it will be helpful for multiple error correction ECC to be applied to next-generation communication and memory systems.
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