ATM 스위치에서 셀 순서 재 정렬 방식에 관한 연구

박성헌 朝鮮大學校 大學院 1998 국내석사

The future B-ISDN(Broadband Integrated Services Digital Network) will support a wide variety of communication services with different QoS (Quality of Services) requirements The ATM(Asynchronous Transfer Mode), because of its efficiency and flexibility, is widely accepted as the basis for the future B-ISDN Recently, research and development for realizing commercial ATM switching systems for broadband ISDN have been active worldwide. One of the important issue in these activities is the design issue of ATM switch fabrics that is related to the speed The ATM switches are required to support lines at the speeds of several Gbps It is expected that ATM switch fabrics will be implemented using very high-speed devices including those for the optical switching and highly parallel processing architectures with latest VLSI technologies. But the parallel switch architecture has the out-of-sequence problem To solve this problem, the time-stamp method and the cell sequence aligning memory method were proposed by NEC Corporation. But the former has unnecessary delay time to resequence, and the latter has the continuous out-of-sequence which is occurred by the signal loss between the cell counter and the comparator, by the overflow because of the fixed buffer size We have studied the out-of-sequence problem due to the cell transfer delay and the overflow due to the diffident cell transfer delay for the parallel ATM switch fabric and the fixed buffer size in the switch fabric Then, we propose the new ATM switch architecture to fix the out-of-sequence in the parallel ATM switch fabric Also, we solve two problems in the parallel ATOM switch using the time-stamp method and the cell sequence aligning memory method.

셀 추출 Banyan Network의 출력 버퍼 설계에 관한 연구

최정석 숭실대학교 1998 국내석사

ATM 스위치에서 트래픽 특성별 버퍼관리 스케쥴링에 관한 연구

최현호 조선대학교 대학원 1997 국내박사

The future B-ISDN(Broadband Integrated Services Digital Network) will support a wide variety of communication services with different QoS (Quality of Services) requirements. The ATM(Asynchronous Transfer Mode), because of its efficiency and flexibility, is widely accepted as the basis for the future B-ISDN. In ATM networks, various types of traffic are statistically multiplexed to efficiently utilize the network resources. But, since the services in ATM networks are very various and the characteristic of traffic generated from each application service source is very different from each one, shared buffer mechanism, that shares only one buffer, cannot guarantee QoS, requirements for traffics. So, in ATM networks, it is difficult for the existing scheme sharing a buffer to guarantee the QoS of each traffic and to control the scheduling of mixed cells stored in the buffer due to the various service and the different traffic characteristics of each service. In this paper, we proposed the mechanism for the buffer management scheduling method with the separated buffer for traffic characteristics in the ATM switch, and analyzed the cell loss probability and the delay of each traffic (CBR/VBR/ABR) based on the weighted value and the dynamic cell scheduling algorithm. The proposed switch buffering model classifies composite traffic incoming to the switch, according to the characteristic of traffic, then stores them in the logically separated buffer, and adopts the round-robin services with weighted value in order to transmit cells in buffer through one output port. We analyzed 4 cell serviced scheduling algorithm with dynamic round-robin for each logically separated buffer, in which buffers have the respective weighted values and 3 classes of mixed traffic which characterized by cell descriptor. In simulation, using SIMCRIPT II.5, we model the VBR and the ABR traffic as ON-OFF processes, and the CBR traffic as Possion processes. As the results of analysis according to the proposed buffer management mechanism and cell services algorithm, we have found that the required QoS of each VC can be guaranteed depends on a scale of weighted values allocated to buffer, VC buffers that changed the weighted values, and cell scheduling algorithm.

ATM스위치에서 동적 버퍼할당 방식에 관한 연구

정운석 朝鮮大學校 産業大學院 1998 국내석사

Most of traffic in the ATM network have the bursty characteristics. As there is a unused bandwidth on the real time, that has the bandwidth waste. Also, If there is a traffic congestion in the ATM network, that is able to have the connection delay and the cell loss. To resolve this congestion, we need the output-buffered priority traffic control method. In this paper, we improved the multiplexing benefit by tracking the real tune bandwidth capacity on the link, and we guarantee the cell loss and the cell delay by allocating buffer dynamically according to the condition of buffer.

ATM 스위치 네트워크에서 사용 대역폭 할당 방법에 관한 연구

한상옥 조선대학교 대학원 1999 국내박사

The existing resource management schemes for QoS guarantee of each service class are classified as ABR traffic control scheme and 1-pass service bandwidth policing scheme in ATM network. The these schemes endow the highest priority to CBR traffic, middle priority to VBR traffic and the lowest priority to UBR/ABR traffic, 1-pass service policing scheme can guarantee the QoS of CBR/VBR traffic, but is not proper for ABR service requiring the residual bandwidth. ABR traffic control scheme must use 2-pass service policing scheme for guaranteeing MCR of ABR service. A switch allocates the proper bandwidth for each service class in the first pass of 2-pass service policing scheme. In order words, a switch allocates PCR. for CBR service, SCR for VBR service and MCR for ABR service. Because network admits ABR traffic in the limit of not affection the Qos of CBR/VBR traffic, it can guarantee the Qos of CBR/VBR traffic. Also, 2-pass service policing scheme can increase the utilization of network as using residual bandwidth and support fair service to each use. The important element of 2-pass algorithm measures ER by exactly grasping the used bandwidth of network and adjusts transmission rate as conveying ER information to source through RM cell. Therefore, this scheme can efficiently use the residual bandwidth of network and guarantee cell loss and fairness.

廣帶域 ISDN의 ATM스위치 構造에 關한 硏究

김규훈 漢陽大學校 1990 국내석사

Batcher-Banyan형 ATM스위치의 성능개선에 관한 연구

이원재 崇實大學校 情報科學大學院 1994 국내석사

셀프 라우팅 ATM스위치에서의 Deadlock회피에 관한 연구

김민중 弘益大學校 大學院 2003 국내석사

광대역 정보통신망(B-ISDN)은 고용량의 데이터를 빠른 속도로 전달하는 망이다. 최근의 데이터는 고용랑의 빠른 전송을 요구하므로 B-ISDN은 많은 분야에서 이용되고 있다. 대부분의 B-ISDN Application은 기존의 점대점(Point-to-Point)통신뿐만 아니라 Multicast 통신을 요구하고 있다. 이 논문에서는 짧은 정해진 사이즈의 Multicast Header로 형성되는 Packet과 Multicast Routing을 위하여 Restricted Address Encoding Scheme을 기초로 하는 알고리즘에 대하여 그 문제점을 파악한다. 또한 Multiple Multicast Packet의 경우 Deadlock이 발생할 가능성을 배제할 수 없다. 본 논문에서는 이러한 경우에 사용되는 ATM스위치를 페트리 네트를 이용하여 모델링(Modeling)한 후 Reachability 그래프를 그리고 Critical상태와 Deadlock상태를 파악하고 Critical상태에서 Deadlock 상태로 되는 것을 막기 위하여 특정 포트에 우선권을 부여함으로써 Deadlock을 회피함으로써 정보 흐름을 원활하게 한다. Nowadays, in B-ISDN, Point-to-Point Service has been very important service. In this thesis, we discuss the multicast communication in the self-routing MIN(multistage interconnection network) for constructing the internal architecture of ATM(Asynchronous Transfer Mode) switches. The banyan switches are modeled using Petri Net with Inhibitor Arc. Using reachability graph, critical and deadlock states are identified. In order to prevent Banyan switches from entering deadlock state, specific output ports are prioritized. Using Inhibitor Arc, certain ports are prioritized to prevent banyan switches from occurring deadlock situation.

셀 추출 Banyan 네트워크에 관한 연구

장석진 崇實大學校 情報科學大學院 1995 국내석사

공유 다중 버퍼 ATM 스위치에서의 메모리 컨트롤러 설계

강운천 弘益大學校 大學院 2001 국내석사

Shared multibuffer ATM switches have advantage on the size and access speed of buffer memories compared with input or output buffer switches since they can extend memory bandwidth by the use of multiple independent buffer memories. In this paper, a simple hardware controller was designed for control of input and output cross switches. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, controllers have been made with a simple control circuit.