멀티코어 시스템의 효율적인 메모리 시험을 위한 캐시 적중률 감소 방안 = Reducing Cache Hit rate for Efficient Memory Test of Multicore Systems

다국어 초록 (Multilingual Abstract)

Multi-functions and high performances of digital devices have been required to increase the complexity of the internal components. As a result of these changes, the accurate diagnosis for each component becomes more important. In general, the main memory test is not accurate diagnosis due to the cache memory. In this paper describes the cause of low memory test accuracy and proposes a method for improving the accuracy of memory test.
The proposed method, random pattern with large block test, is the way to create randomly with increasing the block size of the test pattern. As an experiment result, it reduces the cache hit rate and it is able to more main memory accesses. Thus, proposed method will be expected to high accuracy of memory test and ensuring the reliability of the product by correct diagnosis.
But it is not perfect method. In order to more accurate memory test, creating the test pattern that lots of bit transitions and changing the test address randomly like operating systems are necessary.

목차 (Table of Contents)

• 1. 서론 1
• 2. 관련 배경 5
• 3. 기존 연구 12
• 4. 캐시 적중률 감소 방안 15
• 5. 실험 및 결과 20
• 5.1 고정 패턴 실험 21
• 5.2 랜덤 패턴 실험 23
• 5.3 라지 블록 랜덤 패턴 실험 27
• 6. 결론 34
• 참고문헌 36