20Gb/s NRZ Receiver Equalizer With Feed-Forward CTLE and Inverter Based Summer DFE in 28nm CMOS Process

다국어 초록 (Multilingual Abstract)

This thesis includes CTLE(Continuous Time Linear Equalizer) and DFE(Decision Feedback Equalizer) for 20Gb/s. As the speed of the interface and the length of the channel increases, the importance of equalizers emerges. For CTLE, a Feed-Forward pass was introduced. A larger gain boosting was obtained at a high frequency, and 13 dB gain was obtained at 10 GHz. In addition, a differential inductor was introduced to operate at 20Gb/s. Octagonal form inductor was designed to have Inductance: 1.278nH, Q factor: 16.33, and area: 0.26. In the case of DFE, by introducing summer as an inverter, contrary to the exisitng CML(Current Mode Logic) type current summing method, it was implemented with low power, small area. Max Eye Width of 0.803 UI was obtained from BER(Bit Error Rate). This thesis is based on 28nm CMOS(Complementary Metal Oxide Semiconductor) process with FDSOI(Fully Depleted Silicon On Insulator).

목차 (Table of Contents)

• 1 Introduction 2
• 2 Background 6
• 2.1 Conventional Continuous Time Linear Equalizer 6
• 2.1.1. CTLE pole & zero and Frequenct Response 7
• 2.1.2. Channel & CTLE Frequency Response Reraltionship 8
• 2.2 Conventional Decision Feedback Equalizer 10
• 2.2.1. PRBS Data 10
• 2.2.2. ISI(InterSymbol Interference) 12
• 2.2.3. DFE(Decision Feedback Equalizer) 13
• 2.2.4. Summer 15
• 2.2.5. Slicer 16
• 2.2.6. DFE Time Margin 19
• 3 Proposed CTLE & DFE Architecture 20
• 3.1 Octagonal Differential Inductor Automation Layout Code 20
• 3.2 Proposed Feed-Forward CTLE (FF-CTLE) 23
• 3.2.1. Channel Specification 24
• 3.2.2. Feed-Forward CTLE Path 25
• 3.3 Proposed DFE With Inverter Based Summer 27
• 3.3.1. Inverter Based Summer 27
• 3.3.2. Low CLK-to-Q Delay StrongArm Latch & SR Latch 33
• 3.4 Overall Architecture 35
• 4 Simulation and Measurement Result 38
• 4.1 Simulation Result 38
• 4.1.1. Channel Simulation 38
• 4.1.2. Inductor Simulation 39
• 4.1.3. CTLE Simulation 40
• 4.1.4. DFE SA Latch & SR Latch Simulation 43
• 4.1.5. FF-CTLE & DFE Overall Simulation 44
• 4.2 Measurement Result 47
• 5 Conclusion 50
• Reference 51