2.3GHz CMOS 2단 저잡음 증폭기설계 및 제작에 관한 연구 = A study on the design and fabrication of a 2.3GHz CMOS 2-stage Low Noise Amplifier

국문 초록 (Abstract)

영문초록:Recently, wireless communication WiBro which is one of the next generation technology is not long to get ready to service. When the WiBro service is available, we can use various kinds of information and contents at high speed by connecting internet regardless of time and place. In this paper, we designed LNA in the range of 2.3GHz WiBro by applying 0.25um CMOS technology. In advance of amplifier simulation, we applied inductor to PGS structure which is always mentioned because of its physical size and Q factor in order to increase the area efficiency of the whole chip while enhancing the series resistance of inductor and Q factor. Designed amplifier induced each of the voltage without making any bias circuit. At this time, we turned on electricity of 30mA. We put the inductance value by choke inductor to prevent leakaging out of AC toward in/output matching and bias. And we put a capacitor and made a DC block. As a result, in the simulation data, the gain is 26.84dB and the noise figure showed to be 3.4dB. In the actual made result, the gain is 23.87dB and the noise figure turned out to be 3.6dB and showed a little error compared to the simulation data. Size of the made amplifier has 940um in width and 720um in length