In this paper, the characteristics according to the channel junction condition between n- and p-type layers of the thyristor random access memory (TRAM) is investigated by using technology computer aided design (TCAD) simulation. Simulation studies ar...
In this paper, the characteristics according to the channel junction condition between n- and p-type layers of the thyristor random access memory (TRAM) is investigated by using technology computer aided design (TCAD) simulation. Simulation studies are performed with the TRAM having a vertical polycrystalline silicon (poly-Si) channel. From the simulation results, the TRAM device has the on/off current ratio (>10<SUP>4</SUP>) reduced by 3 orders compared with the results without BTBT effect, and it is confirmed that fast write speed (< 8 ns) and non-destructive read operation are maintained.