This paper is an investigation of the design of combinational logic circuits which require a minimal number of fault detection tests.
Based on the path sensitizing concepts, the patterns for the primary input gates of the network are defined, and th...
This paper is an investigation of the design of combinational logic circuits which require a minimal number of fault detection tests.
Based on the path sensitizing concepts, the patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network structures, the minimal complete test sets for fan-out free combinational networks can be found easily.
It is also shown that, taking into account the fanout paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.