저전력 24㎓ 저잡음 증폭기 개발

다국어 초록 (Multilingual Abstract)

This paper presents low-power 24-㎓ CMOS low noise amplifier(LNA). This circuit is implemented using 65-㎚ RF CMOS process(f<SUB>T</SUB>/f<SUB>MAX</SUB>=70/90㎓). The low noise amplifier is powered by 1.2V supply, and it is designed to operate at the operation frequency of 24㎓. The proposed LNA has cascode scheme to decrease power consumption and to increase voltage gain, and it is optimized to minimize noise figure. This circuit is applicable to 5th generation(5G) mobile communication network and automotive collision avoidance radar system. The proposed circuit showed the lowest power consumption of 4.2㎽ and the smallest die area of 0.5×0.5㎟. This circuit also showed high voltage gain of approximately 31㏈, low noise figure of 2.71㏈, but it need to improve linearity for IIP3 of 2.8㏈m as compared to conventional research results.