A 0.5–2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

다국어 초록 (Multilingual Abstract)

This paper presents a fast-lock dual-loop successive approximation register-controlled dutycycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider dutycycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast dutycycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ±0.86 % for a wide input duty-cycle range of 15?85 % over a wide frequency range of 0.5?2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-μm, 1.8-V CMOS process and occupies an active area of 0.075 mm².

목차 (Table of Contents)

• Abstract
• I. INTRODUCTION
• II. PROPOSED DUAL-LOOP SAR-CONTROLLED DCC ARCHITECTURE
• III. EXPERIMENTAL RESULTS
• IV. CONCLUSIONS
• REFERENCES