1 J. Mangino, "Using DMA with high performance peripherals to maximize system performance" Texas Instrument 2007
2 S. Liao, "Storage Assignment to Decrease Code Size" 18 (18): 235-253, 1996
3 S. Liao, "Storage Assignment to Decrease Code Size" 186-195, 1995
4 STMicroelectronics, "STM DMA API"
5 V.K. Nandivada, "SARA: combining stack allocation and register allocation" 232-246, 2006
6 D. Bartely, "Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes" 22 (22): 101-110, 1992
7 C. Lee, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems" 330-335, 1997
8 Fujitsu, "FR80S/T series DMA access speed"
9 Samsung, "Exynos 4 quad"
10 J. Barth, "Embedded DRAM design and architecture for the IBM 0.11um ASIC offering" 46 (46): 675-680, 2002
1 J. Mangino, "Using DMA with high performance peripherals to maximize system performance" Texas Instrument 2007
2 S. Liao, "Storage Assignment to Decrease Code Size" 18 (18): 235-253, 1996
3 S. Liao, "Storage Assignment to Decrease Code Size" 186-195, 1995
4 STMicroelectronics, "STM DMA API"
5 V.K. Nandivada, "SARA: combining stack allocation and register allocation" 232-246, 2006
6 D. Bartely, "Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes" 22 (22): 101-110, 1992
7 C. Lee, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems" 330-335, 1997
8 Fujitsu, "FR80S/T series DMA access speed"
9 Samsung, "Exynos 4 quad"
10 J. Barth, "Embedded DRAM design and architecture for the IBM 0.11um ASIC offering" 46 (46): 675-680, 2002
11 V. Zivojnovic, "DSPStone- A DSP oriented Benchmarking Methodology" 1994
12 ARM, "CoreLink DMA Controllers"
13 P. Shivakumar, "CACTI 3.0: an integrated cache timing, power and area model" HP Labs 2001
14 ARM, "ARM architecture reference manual"