Timing Analysis Techniques Review for sub-30 nm Circuit Designs

다국어 초록 (Multilingual Abstract)

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

참고문헌 (Reference)

1 F. Wang, "Variation-aware Resource Sharing and Binding in Behavioral Synthesis" 79-84, 2009

2 Y. Chen, "Tolerating Process Variation in High-Level Synthesis Using Transparent Latches" 73-78, 2009

3 J.Jung, "Timing Variation-aware High- Level Synthesis Considering Accurate Yield Computation" 207-212, 2009

4 B. C. Paul, "Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits" 780-785, 2006

5 C. Hongliang, "Statistical timing analysis under spatial correlations" 24 (24): 1467-1482, 2005

6 Xin Li, "Statistical Performance Modeling and Optimization" Lightining Source Inc 2007

7 Y.Xie, "Statistical High-Level Synthesis under Process Variability" 26 (26): 78-87, 2009

8 S. Bhardwaj, "Scalable model for predicting the effect of negative bias temperature instability forreliable design" 2 (2): 361-371, 2008

9 Sang Phill Park, "Reliabiliability Implications of Bias-Temperature Instability in Digital ICs" 26 (26): 8-17, 2009

10 L. Cheng, "Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources" 250-255, 2007

11 M. B. da Silva, "NBTI-aware technique for transistor sizing of high-performance CMOS gates" 1-5, 2009

12 B. Vaidyanathan, "NBTI-aware statistical circuit delay assessment" 13-18, 2009

13 C. Robert, "Monte Carlo Statistical Methods" Springer 2005

14 D. R. Bild, "Minimization of NBTI Performance Degradation Using Internal Node Control" 148-153, 2009

15 E. Pebesma, "Latin Hypercube Sampling of Gaussian random fields" 41 (41): 303-312, 1999

16 "ITRS 2009 Design Roadmap"

17 A. Singhee, "From Finance to Filp flops: A Study of fast quasi-Monte Carlo methods from Computational finance applied to Statistical Circuit Analysis" 685-692, 2007

18 C. Visweswariah, "First-Order Incremental Block-Based Statistical Timing Analysis" 25 (25): 2170-2180, 2006

19 K. Gulati, "Fast Circuit Simuation on Graphics Processing Units" 403-408, 2009

20 X. Zhou, "DCCB and SCC based Fast Circuit Partition Algorithm for Parallel SPICE simulation" 1247-1250, 2009

21 X. Li, "Asymptotic Probability Extraction for Nonnormal ePerformance Distributions" 26 (26): 16-37, 2007

22 R. Kanj, "An Elegant Hardware-corroborated Statistical Repair and Test Methodology for Conquering Aging Effects" 497-504, 2009

23 S. Tsukiyama, "A statistical static timing analysis considering correlations between delays" 353-358, 2001

24 S. H. Kulkarni, "A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering" 39-46, 2006