The transceiver for USB2.0 interface was designed with Verilog and synthesized to enhance design portability. The proposed transmitter (TX driver) generates 0 ~ 400 mV output and implemented using tri-state inverter cell and FSM (Finite State Model). ...
The transceiver for USB2.0 interface was designed with Verilog and synthesized to enhance design portability. The proposed transmitter (TX driver) generates 0 ~ 400 mV output and implemented using tri-state inverter cell and FSM (Finite State Model). The transmitter driver employs a differential voltage-mode architecture with a variable output voltage swing and includes a pre-driver. The transmitter satisfies the USB2.0 eye-mask specification in the measured eye diagrams. The transmitter consumes 9mW at 1 V supply.