Sub-Threshold 회로를 이용한 초 저 전력 32-비트 파이프라인 MAC(multiplication-and-accumulation) 회로 설계

다국어 초록 (Multilingual Abstract)

This paper proposes an ultra low-power 32-bit pipelined MAC(multiplication-and-accumulation) unit which is operated by MOS transistor for reducing power consumption in sub-threshold region. In the proposed circuit, MOS transistor is operating in the sub-threshold voltage to reduce the power consumption. The designed MAC unit has modified Booth algorithm and three stage pipeline structure. The number of transistor is reduced by 10% with proposed 4-2 compressor. The validity and effectiveness are verified through the HSPICE simulation. The proposed circuit is operated at 166㎻@500㎑ under the 0.4V supply voltage.

참고문헌 (Reference)

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