MIMO-OFDM System을 위한 효율적인 IFFT/FFT 알고리즘 및 하드웨어 설계

다국어 초록 (Multilingual Abstract)

This thesis proposes a variable point IFFT/FFT algorithm and implementation architecture which has capability of supporting 4x4 MIMO-OFDM wireless communication systems. As the main technology, multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) is used for high data transmission of IEEE 802.16m mobile WiMAX system. The MIMO-OFDM is strong in multipath fading channel environment and has an advantage to grow system capacity without increasing bandwidth. So, it can be a solution for frequency limit. In contrast, MIMO-OFDM should solve the problem that increases hardware complexity due to having many data path compared with single-input single-output OFDM (SISO-OFDM). Particularly, Fast Fourier transformation (FFT) is one of the processors which have the biggest complexity in the MIMO-OFDM system. Therefore, it is necessary to design optimum FFF/IFFT processor which can provide 1024/2048-point variably for the IEEE 802.16m mobile WiMAX system.
In this thesis, an area-efficient FFT processor is proposed for IEEE 802.16m next generation mobile WiMAX systems. The proposed scalable FFT processor can support the variable length of 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed scalable 4 path 1024/2048 IFFT/FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using Altera Startix IV FPGA. With the proposed architecture, the logic count for the processor is 7,824 ALUTs and the size of memory is 752,384bits, which are only 28.3% and 60.4%, respectively, compared with those of the 4-channel radix-22 SDC Altera FFT processor.

목차 (Table of Contents)

• 제 1 장 서론 1
• 1.1 연구 배경 1
• 1.2 연구의 내용 및 범위 5
• 1.3 논문의 구성 5
• 제 2 장 관련 연구 7
• 2.1 OFDM (Orthogonal Frequency Division Multiplexing) 7
• 2.2 OFDM 변복조 8
• 2.3 MIMO-OFDM 14
• 2.3.1 ML 신호 검출 기법 16
• 2.3.2 QRM-MLD 심호 검출 기법 17
• 제 3 장 FFT 알고리즘 21
• 3.1 개요 21
• 3.2 FFT 알고리즘 24
• 3.2.1 Cooly-Tukey FFT Algorithm 24
• 3.2.2 Good-Thomas FFT 알고리즘 25
• 3.2.3 Radix-2 FFT 알고리즘 26
• 3.2.4 Radix-4 FFT 알고리즘 28
• 3.2.5 FFT의 Multi-dimension 분해 알고리즘 31
• 3.2.6 Radix-22 FFT 알고리즘 37
• 3.2.7 Radix-24 FFT 알고리즘 39
• 3.3 제안된 Radix-4/4/4/4/4/2 FFT 알고리즘 40
• 3.3.1 Radix-4/4 FFT 알고리즘 40
• 3.3.2 Radix-4/2 FFT 알고리즘 42
• 3.3.3 Radix-4/4/4/4/4/2 44
• 제 4 장 FFT 구현 49
• 4.1 FFT 구현 알고리즘 49
• 4.1.1 기존의FFT 구현 알고리즘 49
• 4.1.2 R2MDC (Radix-2 Multi-path Delay Commutator) 50
• 4.1.3 R2SDF (Radix-2 Single-path Delay Feedback) 51
• 4.1.4 R4MDC (Radix-4 Multi-path Delay Commutator) 52
• 4.1.5 R4SDF (Radix-4 Single-path Delay Feedback) 52
• 4.1.6 R4SDC (Radix-4 Single-path Delay Commutator) 53
• 4.1.7 R22 SDC (Radix-22 Single-path Delay Commutator) 53
• 4.2 제안 FFT 알고리즘의 구현 및 설계 54
• 4.2.1 Radix-2 Multipath Delay Commutator의 동작 55
• 4.2.2 제안 알고리즘의 Radix-4 Multipath Delay Commutator의 동작 56
• 4.3 구현 구조의 SQNR(Signal to Quantization Noise Ratio) 62
• 4.4 VHDL 설계 및 Simulation 63
• 4.5 구현 결과의 복잡도 비교 66
• 제 5 장 결론 및 향후 연구 68
• ABSTRACT 75
• 감사의 글 77