1 "VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity Check Codes" 25-36, Sept.2001
2 "Trellis-Based Decoding of High-Dimensional Block Turbo Codes" 25 (25): 1-8, feb.2003
3 "The π-Rotation Low-Density Parity Check Codes" 2 : 980-984, nov.2001
4 "Soft IP Compiler for a Reed-Solomon Decoder" 25 (25): 305-314, oct.2003
5 "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit" 5 : 58-60, feb.2001
6 "On Finite Precision Implementation of Low-Density Parity-Check Codes Decoder" 4 : 202-205, May2001
7 "Near Shannon Limit Performance of Low Density Parity Check Codes" 32 : 1645-1646, aug.1996
8 "Near Optimum Universal Belief Propagation Based Decoding of Low-Density Parity Check Codes" 50 (50): 406-414, March2002
9 "Low Density Parity Check Codes with Semi-Random Parity Check Matrix" 35 : 38-39, Jan.1999
10 "Low Density Parity Check Codes" it-8 : 21-28, Jan.1962
1 "VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity Check Codes" 25-36, Sept.2001
2 "Trellis-Based Decoding of High-Dimensional Block Turbo Codes" 25 (25): 1-8, feb.2003
3 "The π-Rotation Low-Density Parity Check Codes" 2 : 980-984, nov.2001
4 "Soft IP Compiler for a Reed-Solomon Decoder" 25 (25): 305-314, oct.2003
5 "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit" 5 : 58-60, feb.2001
6 "On Finite Precision Implementation of Low-Density Parity-Check Codes Decoder" 4 : 202-205, May2001
7 "Near Shannon Limit Performance of Low Density Parity Check Codes" 32 : 1645-1646, aug.1996
8 "Near Optimum Universal Belief Propagation Based Decoding of Low-Density Parity Check Codes" 50 (50): 406-414, March2002
9 "Low Density Parity Check Codes with Semi-Random Parity Check Matrix" 35 : 38-39, Jan.1999
10 "Low Density Parity Check Codes" it-8 : 21-28, Jan.1962
11 "Independent Turbo Coding and Common Interleaving Method among Transmitter Branches Achieving Peak Throughput of 1 Gbps in OFCDM MIMO Multiplexing" 26 (26): 375-383, oct.2004
12 "Good Error-Correcting Codes Based on very Sparse Matrices" 45 : 399-431, Mar.1999
13 "Global Standardization of IMT-2000, Emerging Technologies Symposium: Broadband" 10-1, apr.2000
14 "Extended Bit-Filing and LDPC Code Design" 985-989, nov.2001
15 "Efficient VLSI Architectures for Error-Correcting Coding" 2002.
16 "Efficient Encoding of Low-Density Parity-Check Codes" 47 (47): 638-656, feb.2001
17 "Digital Video Broadcasting-Satellite Version 2" 2004
18 "Design of VLSI Implementation-Oriented LDPC Codes" oct.2003.
19 "Analysis of Scaling Soft Information on Low Density Parity Check Codes" 39 (39): 219-221, Jan2003
20 "A Viterbi Decoder with Efficient Memory Management" 26 (26): 21-26, feb.2004
21 "A 54 Mbps (3,6)-Regular FPGA LDPC Decoder" 16-18, oct.2002