Dynamic Voltage Scaler Based on Binary-Weighted Charge Redistribution Digital-to-Analog Converter = 이진가중치 전하 재분배 디지털-아날로그 변환기를 이용한 다이나믹 전압 스케일러

다국어 초록 (Multilingual Abstract)

This paper presents a dynamic voltage scaler architecture based on binary-weighted charge redistributed digital-to-analog (DAC) converter. The proposed architecture uses a DAC as a reconfigurable voltage scaler based on digital control circuit to select the required voltage level. Whereas it is difficult for the conventional voltage converters to scale the output voltage, the output voltage of the proposed architecture can be accurately scaled by the resolution of DAC. The proposed voltage scaler using a 3-bit DAC has been implemented using a 65nm CMOS process. The simulation results with the 3-bit DAC showed accurate 8 output voltage levels of 0 V to 1.05 V from an input voltage of 1.2V. When the proposed voltage scaler was configured to supply 600mV to a 32-bit adder, it showed a small ripple voltage of 10 mV and consumed energy of 4.425 pJ for 6 addition operations during the simulation of 780 nsec.

목차 (Table of Contents)

• Abstract
• I. Introduction
• II. Related Work
• III. Proposed Circuit
• IV. Simulation Result
• V. Conclusion
• Reference