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Chen, Hunglin,Fan, Rongwei,Lou, Hsiaochi,Kuo, Mingsheng,Huang, Yiping The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.
Hunglin Chen,Rongwei Fan,Hsiaochi Lou,Mingsheng Kuo,Yiping Huang 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.
Jong-Il Won,Hyun-Duck Lee,Kui-Dong Kim,Jong-Kee Kwon,Yong-Seo Koo 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, ESD protection circuit with gate-substrate trigger technique for low trigger voltage and low leakage current in 0.13㎛ CMOS process is proposed. The results show that the proposed ESD protection circuit has lower trigger voltage (5.35V) compared with that of conventional GGNMOS protection circuit. And the proposed circuit has lower leakage current (80㎀) compared with that of conventional gate substrate triggered NMOS protection circuit.