공정 코너별 LVCC 마진 특성을 이용한 전력 소모 개선 Voltage Binning 기법

이원준(Won Jun Lee),한태희(Tae Hee Han) 대한전자공학회 2014 전자공학회논문지 Vol.51 No.7

스마트 기기 시장의 눈부신 성장으로 핵심 SoC (System on Chip)에 대한 고성능 다기능 요구와 더불어 전력 소모 또한 급속도로 증가하고 있다. 그러나 이러한 요구 사항을 만족시키기 위해 점점 더 미세화된 공정을 사용하게 되면서 심화된 공정변이(process variation)문제로 인해 설계 마진(design margin)이 증가하여 성능과 전력소모를 악화시켜 궁극적으로 수율에 심각한 악영향을 주고 있다. Voltage binning 기법은 효과적인 post silicon tuning 기법중의 하나로, 개별 칩이 아닌 일정한 범위의 속도와 누설 전류에 따라 칩들을 선별 그룹핑한 bin 단위의 공급 전압 조절을 통해 경제적으로 공정 변이로 인한 parametric 수율 손실을 줄일 수 있다. 본 논문에서는 수율 손실 없이 추가적으로 평균 전력 소모를 개선하기 위한 voltage binning 기반의 최적화된 공급 전압 조절 방법을 제안한다. 제안한 기법은 칩 속도와 누설전류의 특성에 따른 공정 코너들의 서로 다른 LVCC (Low VCC) 마진을 고려하여 전압 마진의 편차를 최적화함으로써 전력 소모를 개선할 수 있다. 제안한 방식을 30나노급 모바일 SoC 제품에 적용한 결과 전통적인 voltage binning 방법 대비 동일조건에서 약 6.8%까지 평균 전력 소모를 줄일 수 있었다. Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li, Chang-Lin,Kim, Hyun Joong,Heo, Seo Weon,Han, Tae Hee The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.6

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

온도변화에 둔감한 저전압용 기준전압 발생기

김필중(Phil Jung Kim) 대한전자공학회 2021 전자공학회논문지 Vol.58 No.11

기준전압 발생기는 반도체 칩이나 전자기기에 필수적으로 사용되고 있으며, 저전력화에 따라서 낮은 전원전압과 온도변화에 대해서도 안정되고 일정한 기준전압을 공급해야 한다. 본 연구에서는 별도의 추가적인 온도보상 회로를 포함하지 않으면서 온도에 둔감한 기준전압을 발생하는 저전압용 기준전압 발생기를 제안한다. 또한 제안하는 기준전압 발생기는 동작 신호가 인가될 때만 기준전압을 발생하도록 설계하였다. 제안한 기준전압 발생기는 동작 신호가 인가된 이후 0.9ns 이내에서 빠르게 동작하고 비교적 매우 안정된 온도계수(7.65ppm/℃)를 나타내어 전원전압 1.5V의 저전압용 반도체 칩이나 전자기기에 적용 가능함을 확인하였다. The reference voltage generator is essentially used in semiconductor chips or electronic devices. In accordance with low power consumption, it is necessary to supply a stable and constant reference voltage even with low power supply voltage and temperature variation. In this study, we propose a low-voltage reference voltage generator that generates a temperature-insensitive reference voltage without including an additional temperature compensation circuit. Also, the proposed reference voltage generator is designed to generate a reference voltage only when an operating signal is applied. The proposed reference voltage generator operates quickly within 0.9ns after the operation signal is applied and shows a relatively very stable temperature coefficient (7.65ppm/℃), confirming that it can be applied to low voltage semiconductor chips or electronic devices with a power voltage of 1.5V.

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

H. V. Nguyen,Youngmin Kim 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.1

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high–frequency conditions (i.e., 100 MHz).

Three-Phase Line-Interactive Dynamic Voltage Restorer with a New Sag Detection Algorithm

Jong-Kyou Jeong,Ji-Heon Lee,Byung-Moon Han 전력전자학회 2010 JOURNAL OF POWER ELECTRONICS Vol.10 No.2

This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3㎸A rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2㎳ delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers, communications equipment, and automation equipment.

Three-Phase Line-Interactive Dynamic Voltage Restorer with a New Sag Detection Algorithm

Jeong, Jong-Kyou,Lee, Ji-Heon,Han, Byung-Moon The Korean Institute of Power Electronics 2010 JOURNAL OF POWER ELECTRONICS Vol.10 No.2

This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3kVA rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2ms delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers, communications equipment, and automation equipment.

Three-Phase Line-Interactive Dynamic Voltage Restorer with a New Sag Detection Algorithm

정종규,이지헌,한병문 전력전자학회 2010 JOURNAL OF POWER ELECTRONICS Vol.10 No.2

This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3kVA rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2ms delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers,communications equipment, and automation equipment.

Voltage and Frequency Tuning Methodology for Near- Threshold Manycore Computing using Critical Path Delay Variation

Chang-Lin Li,Hyun Joong Kim,Seo Weon Heo,Tae Hee Han 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2–20.0%, compared to existing methods in variation-sensitive NTC environments.

Threshold Voltage Variations Due to Oblique Single Grain Boundary in Sub-50-nm Polysilicon Channel

Jungsik Kim,Taiuk Rim,Junyoung Lee,Chang-Ki Baek,Meyyappan, Meyya,Jeong-Soo Lee IEEE 2014 IEEE transactions on electron devices Vol.61 No.8

<P>We investigate the effect of single grain boundary (SGB) with arbitrary angles on the threshold voltage (V<SUB>th</SUB>) variation in sub-50-nm polysilicon (poly-Si) channel devices using 3-D simulation. An SGB in the poly-Si channel causes changes in potential barrier profile resulting in the variation of V<SUB>th</SUB>. As the planar devices scale down to 20-nm, oblique SGB can significantly increase the whole potential barrier profile and cause large V<SUB>th</SUB> variation. However, due to superior gate controllability, the gate-all-around devices show relatively small increase of the conduction energy band, and thus mitigate the V<SUB>th</SUB> variation even in 20-nm poly-Si channel.</P>

A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter

LEE, Jae-seung,SIM, Jae-Yoon,PARK, Hong June The Institute of Electronics, Information and Comm 2010 IEICE transactions on electronics Vol.93 No.8

<P>A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.</P>