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Design of Efficient Cache Structure for VLIW
Hong, Won-Kee,Kim, Shin-Dug 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
In order to design an efficient cache structure for VLIW architecture, both the memory utilization and the instruction fetch overhead must be addressed. However, the existing caches do not succeed in satisfying these requisite at the same time. In the packed cache, higher memory utilization can be achieved only at the cost of instruction fetch overhead, while in the unpacked cache, the fixed size instruction can simplify the instruction fetch but aggravate the memory utilization. In this paper, a new cache structure called partial-packed cache is proposed to reduce instruction fetch overhead and at the same time achieve high memory utilization. It contains instructions, each of which consists one or more fixed size sub-instruction. The potentials of the partial-packed cache for performance improvement is examined via analytical model. The experimental results show that the best performance can be achieved in the memory system composed of the partial-packed cache as the 1st level cache and the full-packed cache as the 2nd level cache.
Kwon, Jin Ho,Lee, Jae Shin,Kim, Suki 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
In this, paper we propose a programmable digital Automatic Gain Controller(AGC). Compared with conventional analog AGCs which have difficulties in integration due to large capacitors, the proposed AGC can be easily integrated. The digital AGC has a better performance in temperature variation, power supply variation, and substrate noise than the analog AGCs do. In addition, to prevent malfunctions of the AGC caused by noise a mal-function preventer is newly proposed. In order to achieve an optimized time constant of the AGC, we have designed a function block which controls up-down counting clock. This is directly related to the changing speed of the AGC gain. Implemented in a 0.25 ㎛ CMOS process, the AGC operates from a single 2.5V power supply with the dynamic range of 36.1dB.
A 10-bit, 40Msamples/s Foldidng & Interpolating A/D Converter with Wide Range Error Correction
Kim, Tae-hyoung,Sung, Jun-jey,Kim, Soo-hwan,Lim, Shin-il,Kim, Suki 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
This paper describes an 10-bit, 40Msamples/s CMOS folding and interpolating analog-to-digital converter(F&I ADC). A new cascading-folding architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. In order to reduce the nonlinear switch errors related to the sample-and-holder, a charge-pump circuit is used. Furthermore, by using a Wide range error correction scheme, the relaxed design of comparators is possible. The coarse comparators with offsets as large as ±7.8mV are tolerable due to this wide range error correction scheme. The ADC was designed using a 0.25 ㎛ 1-poly 5-metal CMOS process. It consumes 62mW at 40Msamples/s. The INL/DNL is less than ±0.5LSB/±0.4LSB by MATLAB pre-simulation
Design of a Shared Multi-buffer ATM switch with enhanced throughput in multicast environments
Lee, JongIck,Sohn, JongMoo,Lee, MoonKey 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
We propose a shared multi-buffer ATM switch, in which each unicast cell has chances to be read from a shared buffer during three consecutive read cycles and each multicast cell is read from a shared buffer if the shared buffer is not accessed for read of a unicast cell at the last read cycle. The HOL effect that the unicast cells experience is not augmented by the multicast cells and utilization rate of the output ports is increased because both a unicast celll and a multicast cell have the opportunity to be read for each output port. For a fixed multicast rate, the proposed scheme shows 98.9% throughput even though the offered load reaches 1. We designed the proposed shared multi-buffer ATM switch in 0.6um single-poly triple metal CMOS technology. The designed shared multi-buffer ATM switch has 8 x 8 ports and operates at 20MHz, which supports 155.52Mbps STM-1 source rate for each port.
Design of Real-Time Image Enhancement Preprocessor for CMOS Image Sensor
Jung, Yun Ho,Kim, Jae Seok,Hur, Bong Soo,Kang, Moon Gi 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.
Dual-Precharge Dynamic D-type Flipflops for High-Speed True Single-Phase Clocking
An, Hyun-Joo,Chae, Kwan-Yeob,Ki, Hoon-Jae,Kim, Soo-Won 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
True single-phase clocking(TSPC) Dynamic D-type flipflops(DFF's) are fast, but its master-slave structure results in significant amount of setup time. We propose dual-precharge CMOS DFF's to catch input data promptly. Out simulation showed that the setup time was drastically reduced down to 6.3% of the total delay. Consequently, the total delay time, compared to that of a counterpart TSPC DFF, is reduced by 42%.
Efficient Delay Testing Algorithm for Sequential Circuits with a New Scan Design
Huh, Kyung-Hoi,Kang, Yong-Seok,Kang, Sungho 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
Delay testing is essential for assurance of digital circuit operations. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan flip-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.
15-bit Σ-ΔModulator for ADSL Applications
Suh, Bumsoo,Han, Sang-Chan,Kim, Suwon 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
A 550kHz signal bandwidth 15-bit Σ-Δ modulator for ADSL application has been proposed and designed. The most power efficient 2-1-1 cascade structure is selected and the matching of coefficients is optimized properly. The non-idealities introduced by matching and leakage problems have been minimized by a series of fast-settling high-gain fully differential opamps, in which a special gain-boosting scheme named "self-biased gain boosting" is proposed. Also, the popular clock-doubling scheme is used for reducing size of switch TR's and modified for bit-stream feedback usage. The layout of the whole modulator has been packed into 2 x 1 mm area, using 0.35 ㎛ single-poly three-Metal CMOS technology. The simulation results market 97mW for power consumption, that is almost the half of other conventionals.
A Simulation Study of CBR HDTV Transport Packet Delivery on AAL5
Sohn, JongMoo,Lee, JongIck,Lee, ByungRyul,Kim, ChanGyu,Lee, MoonKey 연세대학교 아식설계공동연구소 2000 Journal of the Research Institute of ASIC Design Vol.7 No.1
We propose the dejittering method against the jitter originated from the cell losses in ATM network when CBR traffic is transferred on AAL5. Cell numbering along with maintaining a timer at receiver side introduces 0.669 times peak-to-peak PDV of the AAL5 PDU to that in ITU-T AAL5 standard, and the AAL5 user-HDTV decoder-receives the same or more error-free transport packets in the proposed algorithm than those in the ITU-T AAL5 standard for the same network simulation environment.