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LPCVD로 증착한 텅스텐 박막의 증착 조건 제어에 의한 접착성 및 저항 특성 향상
노관종(Kwanchong Roh),윤선필(Sunpil Youn),윤영수(Youngsu Youn),노용한(Yonghan Roh) 한국진공학회(ASCT) 2000 Applied Science and Convergence Technology Vol.9 No.4
LPCVD 방식에 의해 산화막과의 접착성이 양호하고 ~10μΩㆍ㎝의 낮은 비저항을 갖는 텅스텐 박막을 성장시킬 수 있었다. 텅스텐의 산화막에 대한 접착성은 기판온도가 높을수록, SiH₄/WF_6 비율이 증가할수록 우수하였다. 특히, 가스 비율이 2인 경우 350℃에서도 텅스텐의 성장이 가능하였으며, β-W의 성장으로 비저항이 높았으나 H₂ carrier 가스를 증가시켜 최소화시킬 수 있었다. 따라서, 텅스텐의 산화막에 대한 접착성 향상을 위해 복잡한 증착 공정이나 부가적인 공정을 사용하지 않고 단순히 증착온도, 가스 비율, carrier 가스 조건을 조절함에 의해 해결될 수 있음을 확인하였다. Tungsten(W) thin films with good adhesion property and low resistivity (~10μΩㆍ㎝) were deposited directly on SiO₂ by LPCVD. The adhesion property of W thin films on SiO₂ improves as the temperature and/or SiH₄/WF_6 gas ratio increase. Specifically tungsten thin films could be deposited on SiO₂ even at 350℃ if the gas ratio of 2 was employed. The resistivity of tungsten thin films deposited at 350℃ was high due to the presence of β-W. However, the resistivity can be minimized by increasing the amount of H₂ gas flow. Therefore, it is shown in this work that the adhesion of tungsten thin films on SiO₂ can be improved simply by controlling the process parameters (e.g., temperature, gas ratio and H₂ flow rate) without employing complex deposition methods or additional glue layers.
금속-산화막-반도체 소자의 계면전하 발생에 미치는 정공과 수소의 역할
노용한 成均館大學校 科學技術硏究所 1996 論文集 Vol.47 No.2
MOS 소자의 게이트산화막에 정공이 트랩핑된 후 계면전하의 발생 메커니즘을 게이트 금속의 종류 및 게이트 인가된 전압의 극성의 함수로써 연구하였다. 기존의 정공 트랩핑에 의한 계면전하의 발생 메커니즘과는 다른 새로운 메커니즘을 확인하였으며, 트랩핑된 정공과 발생된 계면전하의 상관관계는 16 : 1이였다. 본 연구 결과와 기존의 모델들을 토대로 고열전자에 의하여 MOS 소자의 발생하는 계면전하의 발생 메커니즘을 전하와 수소의 역할을 구분할 수 있는 전자주입 fluence의 함수로서 규명하였다. Mechanisms of interface traps induced by hole trapping was investigated as a function of both gate metals and gate polarity applied during the stressing. We find that a new generation mechanism which has not been reported previously, and show that approximately one interface trap is induced by sixteen trapped holes. Based on the current findings, we propose a comprehensive interface-trap generation mechanism which can predict the hot electron effects so that clarify the roles of hydrogen and trapped holes as a function of injection fluences.
김경섭,Yonghan Roh 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.51 No.3
A selective liquid phase deposition (LPD) of silicon dioxide was performed on a nanometer-scaled photoresist pattern fabricated by using an oxygen-plasma downstream-ashing technique. With the selective LPD method, silicon dioxide can be deposited at low temperatures under 50 C without thermal damage. Using the selective-liquid-phase-deposited silicon-dioxide layer as a wet etching mask, we could fabricate 600-nm-scale isolated structures. The LPD silicon dioxide showed excellent step coverage and good surface morphology. Moreover, the maximum capacitance value of the LPD silicon dioxide was 7 pF. The leakage current density of the LPD silicon dioxide was also very low, which indicated that the LPD silicon dioxide was a good insulating material for integrated circuit (IC). These results raise possibilities of fabricating new types of nanometer-scaled trenches and other nanometer-scale silicon-based devices.
펄스 레이저 증착법으로 증착된 MgTiO₃ 박막의 전기적 특성 분석
안순홍(Soonhong Ahn),노용한(Yonghan Roh),이영훈(Younghun Lee),강신충(Shinchung Kang),이재찬(Jaichan Lee) 한국진공학회(ASCT) 2000 Applied Science and Convergence Technology Vol.9 No.3
차세대 마이크로파 유전체 소자에 응용하기 위한 MgTiO₃ 박막을 펄스 레이저 증착법(PLD, pulsed laser deposition)을 이용하여 400~500℃에서 비정질 상태로 실리콘 기판 위에 성장시킨 후 전기적 특성을 분석하였다. PLD로 증착된 MgTiO₃ 박막의 전기적 특성은 성장 시 온도에 의존하였다. 즉, 증착 온도가 낮아짐에 따라 MgTiO₃ 박막 내부에 존재하는 이상정전하 결함 밀도가 증가하였으며, 이들 결함과 실리콘 기판과의 전하교환에 의하여 High Frequency(HF) C-V 곡선이 음의 방향으로 이동하는 현상이 관측된 것으로 사료된다. 또한, 증작 온도간 HF C-V 곡선 이동 폭 및 이상정전하 밀도는 ~100Å 두께의 SiO₂ 중간층을 사용할 경우에 현저히 감소함을 확인하였다. We have analyzed electrical characteristics of the amorphous MgTiO₃ thin films deposited by pulsed laser deposition (PLD) technique with the temperature of 400~500℃. The electrical characteristics of MgTiO₃ films heavily depend on the deposition temperature. We speculate that the density of anomalous positive charge (APC) substantially increases as the deposition temperature lowers, causing the HF C-V curves shift to the direction of the negative gate voltage. We further observed that both the degree of C-V shift as a function of the deposition temperature and the density of APC were minimized by the use of SiO₂ with thickness of approximately 100 Å between MgTiO₃ films and the Si substrate.
Ji Hye Lee,Yonghan Roh,Kyoung Nam Lee,Kyoung Seob Kim,김남훈 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.51 No.III
To avoid the effects of thermal stress on device properties, in sophisticated and multilevel device fabrication low-temperature deposition has been required for interlayer dielectrics (SiO$_2$). We have already researched the fabrication of nanometer-scale line-and-space structures ($\leq$100 nm) by using a plasma downstream ashing technique and liquid phase deposition in previous work. In the liquid phase deposition (LPD) process, silicon dioxide thin films were deposited from a solution of hexafluorosilicic acid (H$_2$SiF$_6$) supersaturated with SiO$_2$ by boric acid (H$_3$BO$_3$) addition. Through plasma ashing and the LPD process, silicon dioxide was deposited under 50 $^\circ$C without damaging the photoresist and the periodic nanometer-scale holes of less than 100 nm could be fabricated by control of the plasma ashing time.
Al / TiO₂ - SiO₂ / Mo 구조를 가진 Antifuse의 전기적 특성 분석
홍성훈(Sunghun Hong),노용한(Yonghan Roh),배근학(Geunhag Bae),정동근(Donggeun Jung) 한국진공학회(ASCT) 2000 Applied Science and Convergence Technology Vol.9 No.3
본 논문에서는 낮은 구동 전압에서 동작하고 안정된 on/off 상태를 갖는 Al/TiO₂-SiO₂/Mo 형태의 안티퓨즈를 제작하였다. 하부전극으로 사용된 Mo 금속은 표면상태가 부드럽고 녹는점이 높은 매우 안정된 금속으로, 표면 위에 제조된 SiO₂의 특성을 매우 안정되게 유지시켰다 또한 TiO₂ 절연막을 SiO₂ 절연막 위에 복층 구조로 증착하여, Ti 금속의 침투로 인한 SiO₂ 절연막의 약화로 동일 두께(100 Å)의 SiO₂ 단일막에 비하여 향상된 절연파괴 전압을 얻을 수 있었다. TiO₂-SiO₂ 이중 절연막을 사용하여 적정 철연파괴전압 및 ON-저항을 구현하였으며, 두께가 두꺼워짐으로 인해 바닥금속의 거칠기의 영향을 최소화시킬 수 있었다. 이중 절연막의 두께는 250 Å이고 프로그래밍 전압은 9.0V이고 약 65Ω의 on 저항을 얻을 수 있었다. This paper is focused on the fabrication of reliable Al/TiO₂-SiO₂/Mo antifuse, which could operate at low voltage along with the improvement in on/off state properties. Mo metal as the bottom electrode had smooth surface and high melting point, and was being kept as-deposited SiO₂ film stable. The breakdown voltage of TiO₂-SiO₂ stacked antifuse was better than that of same-thickness (100 Å) SiO₂ antifuse because of Ti diffusion in SiO₂. The improving breakdown-voltage and on-resistance can be obtained as well as the influence of hillock in the bottom metal is reduced by using double insulator. Low on-resistance (65 Ω) and low programming voltage (9.0V) can be obtained in these antifuses with 250 Å double insulator.
Hyung Jin Kim,Yonghan Roh,Byungyou Hong IEEE 2010 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.9 No.2
<P>The direct and selective assembly of deoxyribonucleic acid (DNA)-templated metal (e.g., Ag, Au, Cu, and Pd) nanowires (NWs) is a key technique for the application to electronic devices and nanowire-based biosensors. In this study, a new technique was developed to carefully control the interval of DNA-templated gold NWs (AuNWs) using surface-patterning techniques. The ¿-DNA molecules were stretched and aligned along 3-aminopropyltriethoxysilane (APS) region formed uniformly by self-assembly and patterned by electron beam lithography process, and then treated by positively charged gold nanoparticles to form DNA-templated AuNWs. ¿-DNA molecule was verified to be immobilized and stretched into parallel lines only on the surface of APS-coated parallel paths by surface-patterning technique, and it was possible to control the interval of DNA-templated AuNWs. Also, DNAs were confirmed to be assembled not on the bare SiO<SUB>2</SUB> region but on the APS region defined by amine groups.</P>